XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 168

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
output signal “low” if its TxFIFO is too full and is incapable of receiving one more complete cell of data from
the ATM Layer processor.
When UNI #2 has been selected for “polling”, UNI #1 will continue to keeps its “TxUClav” output signal “tri-
stated”. Therefore, when UNI #2 is driving its “TxUClav” output pin to the appropriate level; it will be driving
the entire “TxUClav” line, within the “Multi-PHY” system.
“TxUClav_in” input pin of the ATM Layer processor (see Figure 26).
If UNI #2 drives the “TxUClav” line “low”, upon the application of its address on the UTOPIA Address Bus,
then the ATM Layer processor will “learn” that it cannot write any more cell data to this UNI device; and will
deem this device “unavailable”. However, if UNI #2 drives the TxUClav line “high” (during “polling”), then the
ATM Layer processor will know that it can write more ATM cell data into the Transmit UTOPIA Interface block,
of UNI # 2.
Figure 16 presents a timing diagram, that depicts the behavior of the ATM Layer processor’s and the UNI’s
signals during polling.
Figure 16:Timing Diagram illustrating the Behavior of various signals from the ATM Layer processor
and the UNI, during Polling
Notes regarding Figure 16:
1. The Transmit UTOPIA Data Bus is configured to be 16 bits wide. Hence, the data, which the ATM Layer
processor places on the Transmit UTOPIA Data bus, is expressed in terms of 16-bit words: (e.g., W0 - W26.)
2. The Transmit UTOPIA Interface Block is configured to handle 54 bytes/cell. Hence, Figure 27 illustrates
the ATM Layer processor writing 27 words (W0 through W26) for each ATM cell.
3. The ATM Layer processor is currently writing ATM cell data to the Transmit UTOPIA Interface Block, within
UNI #1 (TxUAddr[4:0] = 0x00) during this “polling process”.
4. The TxFIFO, within UNI#2’s Transmit UTOPIA Interface block (TxUAddr[4:0] = 0x02) is incapable of
receiving any additional ATM cell data from the ATM Layer processor. Hence, the TxUClav line will be driven
“low” whenever this particular Transmit UTOPIA Interface block is “polled”.
5. The Transmit UTOPIA Address of 0x1F (e.g., the NULL address), is not associated with any UNI device,
within this “Multi-PHY” system. Hence, the TxUClav line is tri-stated whenever this address is “polled”.
Note:
2.2.1.3.10
In Figure 15, a simple illustration of the “Conceptual Multi-PHY” system consisting of two single-channel UNI
devices was presented. In reality, a given Multi-PHY system can or will consist of numerous “multi-channel”
UNI devices.
Although Figure 26 depicts connections between the Receive UTOPIA Interface block pins and the ATM Layer
processor; the Receive UTOPIA Interface block operation, in the Multi-PHY mode, will not be discussed in this
section. Please see Section _ for a discussion on the Receive UTOPIA Interface block during Multi-PHY
operation.
TxUData[15:0]
TxUAddr[4:0]
ATM Layer Processor “polling” with the XRT94L33
TxUEnB*
The XRT94L33 is an example of this, being a “4-channel” UNI device.
TxUClav
TxUSoC
TxUClk
W27
0x00
1
0x00
1Fh
W0
2
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
0x02
W1
3
0x02
0x1F
W2
4
0x00
W3
5
168
0x00
0x02
W4
6
0x02
0x1F
W5
Consequently, UNI#2 will also be driving the
7
0x02
W6
8
0x02
W7
0x00
9
0x00
0x1F
W8
10
0x00
W9
11
xr
0x00
W10
0x02
12
Therefore, the