CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 110

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
15.1. VREFINT Generator
The VREFINT Generator generates bias signals which are
necessary for the operation of all Analog-Section modules.
Furthermore, it produces a tightly controlled reference volt-
age VREFINT, that is delivered to the BVDD Regulator and
the WAIT Comparator. Via a decoupling resistor it also is
routed to the VREFINT pin.
15.2. BVDD Regulator
The BVDD Regulator generates the 2.5-V BVDD supply volt-
age for the internal PLL/ERM module from the 5-V AVDD. It
derives its reference from the VREFINT Generator.
BVDD must be buffered externally by a 150-nF ceramic
capacitor.
15.3. Wait Comparator
The level on pin WAIT is compared to the internal reference
VREFINT. The state of the comparator output is available as
flag ANAA.WAIT and as WAIT Comparator interrupt source.
Furthermore, the output is available on pin WAITH, so that
the hysteresis of this comparator can be set with an external
positive-feedback resistor (100kOhms min.).
After reset, the module is off (zero standby current). The
module is enabled by setting flag SR0.ADC, together with the
P0.6 Comparator and the ADC. If the VREFINT Generator is
powered up as well (cf. Table 15–1), the user has to assure
15.4. P0.6 Comparator
The level on port P0.6 is compared to AVDD/2. The compar-
ator features a small built-in hysteresis. The state of the com-
parator output is available as flag ANAA.P06 and as P0.6
Comparator interrupt source.
After reset, the module is off (zero standby current). The
module is enabled by setting flag SR0.ADC, together with the
WAIT Comparator and the ADC. If the VREFINT Generator
is powered up as well (cf. Table 15–1), the user has to assure
that the necessary VREFINT set-up time has elapsed,
before using comparator results (flag and interrupt).
The interrupt source output, which must be enabled by set-
ting flag ANAA.EP06, is routed to the Interrupt Controller
logic. But this does not necessarily select it as input to the
Interrupt Controller. Check section “Interrupt Controller” for
the actually selectable sources and how to select them.
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June 12, 2003; 6251-579-1PD
The VREFINT-pin voltage, which has to be buffered exter-
nally by a 10-nF ceramic capacitor, is input to the ADC as
alternative, internally generated, reference voltage.
This module is permanently enabled during reset, in the CPU
modes FAST, PLL and PLL2, and whenever SR0.ADC or
PLLC.PMF is not 0. A certain set-up time has to elapse after
enabling the module for VREFINT to stabilize.
No resistive load must be connected to the VREFINT pin.
This module is permanently enabled whenever PLLC.PMF is
not 0. A certain set-up time has to elapse after enable for
BVDD to stabilize.
An overload condition in the regulator (current or voltage
drop-out) is stored in flag ANAA.BVE. The immediate over-
load signal may be routed to the LCK special output by
selection in field ANAU.LS (UVDD Analog Section).
that the necessary VREFINT set-up time has elapsed,
before using comparator results (flag and interrupt).
The interrupt source output is routed to the Interrupt Control-
ler logic. But this does not necessarily select it as input to the
Interrupt Controller. Check section “Interrupt Controller” for
the actually selectable sources and how to select them.
The WAIT Comparator interrupt source toggles with f
generate interrupts as long as the level on pin WAIT is lower
than the internal reference.
The P0.6 Comparator interrupt source toggles with f
generate interrupts as long as the level on pin P0.6 is lower
than the internal reference.
PRELIMINARY DATA SHEET
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