CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 167

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
The End-of-Telegram interrupt is generated if the Write-FIFO
is empty and the stop condition is completed. The flag BUSY
is zero in this case.
A Write-FIFO-Half-Full interrupt is generated by the Write-
FIFO each time the entry number reduces from 4 to 3 (‘half-
full’ state, WFH flag set), but not before at least two entries
have been transferred from the Write-FIFO to the SR.
Reaching the fill level of 3 entries during re-filling the Write-
FIFO may (but must not) generate an interrupt too.
Those interrupts occurring during re-filling the Write-FIFO
could be a source of problems. They would be served as
soon as the momentary ISR is left. This situation would con-
fuse the ISR seriously, because though the flag WFH is zero,
the Write-FIFO is filled above the half-full level.
The Write-FIFO-Half-Full interrupt is essential as start of a
refill routine. This routine has to guarantee, that at the end
the fill state is definitely > 3 entries. In this way prepared,
again dropping to 3 entries safely triggers the next Write-
FIFO-Half-Full interrupt, starting the next refill routine.
The strategy to obtain a fill state > 3, is to fill up to ‘half-full’
state (WFH flag set), and then to add 2 entries above that.
During this refill routine, all other interrupts have to be dis-
abled. At the end of this refill routine, to avoid ambiguities,
any I
cleared.
26.1.4.2. Example of Operation
The software has to work in the following sequence (ACK=1)
to read a 16-bit word from an I
condition that the bus is not active):
The value 0x21 in the first step results from the device
address in the 7 MSBs and the R/W-bit (read=1) in the LSB.
If the telegrams are longer, the software has to ensure that
neither the Write-FIFO nor the Read-FIFO can overflow.
To write data to this device:
26.1.5. Inactivation
Since the described block is an I
ity stops if the end of a telegram is reached. I
not start any bus activity on their own. However, the block
internal clock is always running at full speed of I
or 5 MHz), independent of the bit rate divider setting. The
standby mode is therefore intended for the lowest possible
power consumption.
Switching off the I
flag in the standby register may result in the output signal
SDAx being drawn to zero for the time the I
To avoid this situation, disable the corresponding port pin as
special output during operation pausing and allow the port to
return to high level.
Micronas
2
C interrupt requests received in meantime, have to be
-write 0x21 to
-write 0xFF to
-write 0xFF to
-read RFE bit from
-read dev. address from
-read RFE bit from
-read 1st databyte from
-read RFE bit from
-read 2nddatabyte from
-write 0x20 to
-write 1st databyte to
-write 2nd databyte to
2
C module by the corresponding enable
2
2
C device address 0x10 (on
C master, all I
I2CWS0x
I2CWD0x
I2CWP1x
I2CRSx
I2CRDx
I2CRSx
I2CRDx
I2CRSx
I2CRDx
I2CWS0x
I2CWD0x
I2CWP0x
2
C module is off.
2
C slaves can-
2
C bus activ-
2
C clock (4
June 12, 2003; 6251-579-1PD
26.1.6. Precautions
Switching off the I
flag in the standby register, and then re-enabling it, may
result in the last transmitted byte being transmitted again. To
avoid this situation, disable the corresponding port pin as
special output during operation pausing. After re-enabling
the module by setting the corresponding enable flag, wait at
least the transmission time of one byte before re-enabling
this special output.
For the effect of CPU clock modes on the operation of this
module refer to section “CPU and Clock System” (see
Table 4–1 on page 37).
Note: The I
side world. This implies that neither logic output low level
switching specs nor logic input value specs of the official I
specification document are literally met. Refer to section
"Ports" for the actual spec values of this implementation.
Fig. 26–2:
Fig. 26–3:
Fig. 26–4:
SDA
SCL
SDA
SCL
SDA
SCL
2
C block uses U-Ports as connection to the out-
Start or Restart Condition I
Single Bit on I
Stop Condition I
1/4T
1/4T
1/2T
2
C module by the corresponding enable
1/2T
1T
1T
3/4T
2
C-Bus
2
C-Bus
CDC 32xxG-C
1/4T
1T
2
C-Bus
repeated
8 times
1/4T
165
2
C