CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 159

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
Table 25–1:
Fig. 25–3:
The level of the start bit is always opposite to the neutral
level. The level of the stop bits is always the same as the
neutral level. If a parity bit is programmed, odd or even parity
can be selected.
Table 25–2:
As a general rule, the parity bit completes the number of
ones in the data field to the selected parity.
25.1.3.3. Compare Address
The content of the Compare Address register UAxCA is com-
pared with each received telegram. On a match, the interrupt
flag ADR is set and the interrupt source signal is triggered.
The MSB of register UAxCA must be set to zero if transmis-
sion of a seven bit data field is configured in register UAxC.
25.1.3.4. Interrupt
Four signals can trigger the UART interrupt source output.
Three of them set their own flags in the Interrupt Flag regis-
Micronas
Module
Name
UART0
UART1
Parity Flag
odd
odd
even
even
S = Start bit
P = Parity bit
S
S
S
S
Examples of Telegram Formats
Module specific settings
HW Options
Item
RX inversion
TX inversion
RX inversion
TX inversion
Definition of Parity Bit
0 1 2 3 4 5 6 7 P
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6
0 1 2 3 4 5 6 7 P
Number of Ones
odd
even
odd
even
T0 = 1. stop bit
T1 = 2. stop bit
Address
UA0
UA1
T0
T0 T1
T0 T1
T0
Parity Bit
0
1
1
0
June 12, 2003; 6251-579-1PD
Initialization
Item
UART0-RX input
UART0-TX output
UART1-RX input
UART1-TX output
ter UAxIF and can be enabled by setting bits in the Interrupt
Mask register UAxIM.
1. When the flag TBUSY in register UAxC is set to zero, the
interrupt source output is triggered. This indicates that a
transmission is finished and the transmit buffer is empty.
There is neither an interrupt flag to indicate this event, nor a
mask flag to disable this interrupt.
2. RCVD is generated by the receive control logic at the end
of each received telegram even if the FIFO is full. This signal
is enabled by setting the corresponding bit in register UAxIM.
3. BRK is generated by the receive control logic each time a
break is detected. This signal is enabled by setting the corre-
sponding bit in register UAxIM.
4. ADR is generated by the address comparator. This signal
is enabled by setting the corresponding bit in register UAxIM.
BRK and ADR also set flags in the Interrupt Flag register
UAxIF when enabled. The first RCVD interrupt, when the
FIFO has been empty before, sets a flag in UAxIF too. Even if
all interrupts are enabled in register UAxIM, the interrupt
source output is triggered only once within a telegram. UAxIF
flags remain valid until the end of the next telegram. ADR is
not generated and the ADR flag is not set if a frame or parity
error was detected in the corresponding telegram.
25.1.4. Operation
With proper HW configuration and SW initialization, a UART
module is ready to transmit and receive telegrams in the
selected format.
25.1.4.1. Transmit
A write access to UART Data register UAxD immediately
loads the transmit shift register and starts transmission with
sending the start bit. The flag TBUSY in register UAxD is set.
At the end of transmission the interrupt source signal is trig-
gered and the flag TBUSY is reset.
To avoid data corruption, ensure that flag TBUSY is LOW
before writing to UAxD
25.1.4.2. Receive
A first negative edge of a telegram on the RX line of a UART
starts a receive cycle and sets the flag RBUSY in UAxC.
After reception of the last bit of the telegram, the telegram
content, together with its status information, is transferred to
the receive FIFO and an interrupt is generated. RBUSY is
resetted. Telegram data are available in register UAxD, tele-
gram status in register UAxC.
Setting
U2.5 special in
U2.4 special out
U2.3 special in
U2.2 special out
CDC 32xxG-C
Enable Bit
SR0.UART0
SR0.UART1
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