CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 192

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
29.2. Functional Description
29.2.1. 3bit-Prescaler
The programmable 3bit-Prescaler supplies the module with
clock signals. It scales down the HW option selectable clock
by factor 1, 2, 3 to 8 (see Table 29–2 on page 192). The out-
put is 64 times the bus clock. The desired input frequency
from the clock divider is hardware programmable.
29.2.2. Internal Clocks
In low power mode the clock supply of the whole module with
exception of the receive bit logic can be stopped. The receive
bit logic needs a clock in low power mode too, because it
must filter and watch the bus line for a wake-up signal.
29.2.3. Transmit T
The transmit T logic sends a continuous stream of T-signs if
active. It outputs a permanent high if it is inactive.
29.2.4. Transmit Bit
Depending on the input signals the transmit bit logic modifies
the T-signs to ones or zeros.
A phase correction can be done by adjusting the start time of
a transmit bit sequence.
Other bus behavior than sending zeros, ones or T-signs may
be forced by the SW using the universal port in normal mode
directly. The bus line may be released or pulled low.
29.2.5. Receive Bit
The receive bit logic samples the bus level at a frequency of
64 times of the bus clock. It filters the input signal and
decodes the input stream to supply the receive telegram
logic with the logical bus signals (0, 1 and T) and the receive
clock. Additional it measures the pulse width of each non T-
sign. It creates a bus reset signal if the active bus is hold
down beyond the end of a bit time. It creates a wake-up sig-
nal if there is a low level on the passive high bus.
29.2.6. Send Telegram
The send telegram logic will be enabled by the transmit FIFO
and the receive telegram logic if four consecutive T-signs
were received. It supports the transmit bit logic with the
transmit bit sequence. If it recognizes the begin of a new
field, it waits one bit time (separator T-sign).
29.2.7. Receive Telegram
The receive telegram logic traces the bus and indicates the
state to the status register and other related modules. The
received bit field is written to the receive FIFO. The receive
telegram logic is active all the time. Even if the module is
transmitting a telegram all bits must be received too in a multi
master system, because arbitration may be lost. Reception
of own telegrams can be disabled (in a single master sys-
tem).
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29.2.8. Collision Detection
The collision detection logic compares each incoming with
the actual outgoing bit. A difference is signaled to the send
telegram logic. If the module is transmitting, the send tele-
gram logic is stopped immediately and the transmit FIFO and
shift register are flushed.
29.2.9. Transmit FIFO
The transmit FIFO has five entry addresses. One for the field
length of address or data field, one for a address byte, one
for a data byte, one for more address bytes and one for more
data bytes. The field length has to be written once before the
corresponding field is entered into the FIFO unless the field
length is not a multiple of 8.
An entry into the address register is inserted into the bus
clock after the reception of 4 consecutive T-signs. An entry
into the data register is inserted into the bus clock after the
reception of a non T-sign and one T-sign. Thus it is possible
to append a second data field (maybe acknowledge) after
the reception of a telegram.
The transmit FIFO may be flushed to abort a transmission. It
is also flushed if the transmit telegram logic is active and a
collision is detected.
29.2.10. Receive FIFO
The receive FIFO will be filled from the receive shift register.
It has two exit addresses. One for the field length and field
type and one for the bit field. The field length has to be read
before the corresponding field is taken from the FIFO. The
receive FIFO will be frozen if it is full. The receive shift regis-
ter will be over written.
29.2.11. Interrupt
Several flags of the status registers are connected by a logi-
cal-or to the interrupt source signal. The interrupt output can
be masked by a flag in the control register.
PRELIMINARY DATA SHEET
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