CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 185

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
The information processing time is the internal processing
time. After reception of a bit (sample point) this time is
needed to calculate the next bit for transmission.
With a baud rate of 1 MBd a bit should be at least 8 t
In case of a triple sample mode (MSAM = 1), the following
boundary condition must also be observed:
The triple sample mode offers better immunity to interference
signals. In the single sample mode a higher transmission
speed is possible.
For high baud rates and maximum bus length, neither SYN
nor MSAM may be switched on. Bosch advises against both
adjustment facilities. When an input filter matched to the
baud rate or a bus driver is used, the triple sample mode is
27.5. Bus Coupling
The bus coupling describes the connection of the internal
signals rx (receive line) and tx (transmit line) to the pins to
the CAN bus.
The output pins are push/pull drivers for TLL levels. The input
pins are also designed for TTL levels.
Integrated transceivers (Siliconix Si9200, Philips 82C250
etc.) are available for physical coupling in the high-speed
range in compliance with ISO/DIS 11898.
For a laboratory system a “minimum bus” can be constructed
by means of a wire-Or circuit.
To utilize the advantages of differential signal transmission,
an analogue comparator is necessary.
Micronas
t
t
t
t
t
t
TSEG2
TSEG2
TSEG1
TSEG1
TSEG1
TSEG1
2 t
t
3 t
t
t
t
SJW
TSEG2
PROP
PROP
Q
Q
+
+
t
t
SJW
SJW
= Information Processing Time
+
2t
Q
June 12, 2003; 6251-579-1PD
Q
long.
not necessary. If SYN is set, synchronization will also be
made with the soft edge (dominant to recessive) and this will
mean higher demands being imposed on the clock toler-
ances.
27.4.2.3. Synchronization
The BTL carries out synchronization at an edge (change of
the bus level) in order to compensate for phase shifts
between the oscillators of the different CAN nodes.
27.4.2.4. Hard Synchronization
Hard synchronization is carried out at the start of a telegram.
The BTL ensures that the first negative edge is in the sync.
seg.
27.4.2.5. Resynchronization
Resynchronization takes place during the transmission of a
telegram. If the BTL detects an edge outside the sync. seg.,
it can lengthen or shorten the bit. If it detects the edge during
TSEG1, t
TSEG2, t
edges lie in the sync. seg. T
can be lengthened or shortened.
Two forms of resynchronization are possible. In normal oper-
ation, synchronization is carried out only with the negative
edge (recessive to dominant). At low transmission speeds,
synchronization can also be carried out with the rising edge
(SYN = 1).
TxD
RxD
Fig. 27–11:
TSEG2
TSEG1
Bus Coupling
is shortened. In this way, it ensures that the
is lengthened. If it detects the edge during
+5V
1
0
0
1
0
1
1
SJW
CDC 32xxG-C
OR
is the maximum time a bit
ITX
tx
REF1
rx
REF0
183