CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 71

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
All stages of the three counters can be selected to generate
an interrupt or a wake-up signal.
The RTC can’t be stopped during debug mode by flag
CR.STPCLK=1.
7.1.2. Polling Module
The Polling Module periodically activates the output signal
Wake Out which can be enabled by SW to drive port H0.2
(Poll Out). The rising edge of the Polling Period input (f
defines the begin and the Polling Clock (f
with the delay counter defines the duration of the high time.
This can be used to cyclically flash a LED or to feed a current
into an external circuit.
The falling edge of the Wake Out signal is used to sample
the input level of all Wake Ports (WPx) which are configured
for high or low level trigger mode. Those configured ports will
set the corresponding WPx flag in register WUS with the fall-
ing edge of the strobe signal.
Please refer to figure 7–5 for timing details about the Wake
Out and the strobe signals.
Due to the adjustment mechanism by the 20-bit reload regis-
ter, the polling period is not always constant. Depending on
the reload value, the polling period may vary between 0.5
and 1.5 nominal polling periods at the point of reloading.
7.2. Registers
RC
r/w1:
r/w0:
XK
r/w1:
r/w0:
Write to zero for future compatibility.
XM
r/w1:
r/w0:
LD
r:
w1:
w0:
SRC
r/w0:
r/w1:
r/w2:
r/w3:
Writing to SRC does not select a new oscillator source
immediately. This will be done automatically together with
Micronas
r/w
OSC
RC
1
7
XK
1
6
4MHz XTAL
Load SRC and SSC
RC oscillator
enable
disable
External 32kHz XTAL (not available)
enable
disable
always enabled
disabled during power saving modes
Always read as zero
Immediately selects the oscillator source
according to SRC and loads the register SSR
to the SSC.
No action
Oscillator Source Select
4/5MHZ XTAL divided by 8 selected
Don’t use, factory test only
RC oscillator selected
Ground (don’t use for compatibility reasons)
XM
Oscillator Source Register
1
5
x
4
LD
3
No HW reset
x
2
PC
) input together
1
SRC
June 12, 2003; 6251-579-1PD
0
0
Res
Offs
PP
)
The polling period has to be set equal or greater than four
times the polling delay.
7.1.3. Port Wake Module
There is a trigger mode logic (level or edge sensitive) and a
wake source flag for each Wake Port. The Wake Out input is
a signal from the Polling Module. The falling edge generates
a strobe pulse which is used to sample the level of the Wake
In input and set the corresponding wake source flag if neces-
sary.
(WSC.AST=1), if there is no RTC subsystem (with Polling
Logic) implemented. The corresponding WPx flag in register
WUS will be forced to high as long as the programmed con-
dition (high or low level) is met at the Wake Port. Please see
figure 7–6 for details. The selected strobe signal source is
valid for all Wake Ports. Mixing of the strobe signal sources
(polling and alternative) is not possible.
The wake flags of all Wake Ports are located in the wake-up
source register WUS. The trigger events which can set the
wake flags can be configured in the wake-up pin mode regis-
ters WPM0 to 8 either in field MOD0 or MOD1. Please refer
to Table 7–7 for details about allocation of mode registers
and Wake Ports.
The output of each Wake Port is connected to an or gate,
whose output can generate a Wake Port interrupt as well as
a wake-up signal.
the next reload of the SSC. It can be forced immediately by
writing a one to the flag LD with the same write access. A
read access returns the current source select, not the
requested. Thus read-modify-write instructions have to be
used carefully.
For typical settings refer to table 7–1, the values 0 and 1 are
not allowed. To avoid programming unexpected values,
never write single bytes of the SSR on their own, but always
all 3 bytes without being interrupted by SSC read. This is
necessary, as for reading SSC the register hardware uses
the same buffer registers as for writing SSR. Writing SSR
does not load the SSC immediately. This will be done auto-
matically together with the next reload of the SSC. Immedi-
ate loading of the SCC can also be forced by setting
OSC.LD. Wait one f
to SSR because it lasts one bus cycle until a written value
gets valid.
r/w
r/w
r/w
r/w
SSR
x
x
7
An
alternative
x
x
6
Sub Second Reload Register
x
x
5
IO
cycle between write and read access
No HW reset
x
x
Bit 15 to 8
strobe
4
Bit 7 to 0
CDC 32xxG-C
x
3
signal
Bit 19 to 16
x
2
can
x
1
be
x
0
used
3
2
1
0
Res
Offs
69