CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 196

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
STATE
r:
Table 29–3:
PW
r:
The pulse width of the most recently non T-sign is stored in
this register. It is measured in increments of 1/64 of the bus
clock period.
More bytes of a data field must be written to DGRTMD.
The read part of register DGRTMD is associated with the
front entry in the receive FIFO (the receive field DGRTMA). It
has to be read and interpreted before the corresponding
FIFO entry.
RDL
r1:
r0:
The flag RDL from the status register DGS0 is mirrored here.
It is cleared by a read access to register DGRTMA.
NEM
r1:
r0:
The flag NEM from the status register DGS0 is mirrored
here. FTYP, EOFLD, LEN and register DGRTMA are not
valid if NEM is false.
FTYP
r1:
r0:
EOFLD
r1:
r0:
If EOFLD is set, the corresponding FIFO entry is the last part
of the actual field. The next entry, if there is one, belongs to a
new field.
LEN
r:
The three bit length doesn’t limit the overall length of the cor-
responding field. The length field defines how many bits of
the front entry of the receive FIFO carry valid bits. They are
right aligned (Table 29–4). The real length of the field is
unlimited. The user must count the bytes he fetched from the
FIFO to calculate the real field length.
194
STATE
0 0
0 1
1 0
1 1
w
DGRTMD
r
RDL
0
7
NEM
0
Bus
Passive low
Passive high
Active low
Active high
6
Bus State
State of receive bit logic.
Pulse Width
Pulse width
Receive Data Lost
Data lost
No data lost
Receive FIFO is Not Empty
There is at least one entry.
Empty
Field Type
Address field
Data field
End of Field
Last byte of a field
Not last byte of a field
Length of Field
Length of valid data bit
Receiver States
FTYP
Rx Length & Tx More Data Register
x
5
Transmit More Data
EOFLD
4
x
x
x
3
2
x
LEN2 to 0
x
1
June 12, 2003; 6251-579-1PD
0
x
Res
Table 29–4:
The examples in Table 29–5 illustrate the interpretation of
register DGRTMD. They are valid for an address field (FTYP
= 1) or a data field (FTYP = 0).
Table 29–5:
More bytes of an address field must be written to DGRTMA.
The bytes of a received field must be read from register
DGRTMA. The meaning of this field (address or data) is
defined by the flag FTYP.
Received bytes of a bit field are right aligned. The last byte of
a long bit field (with the LSB) may be filled partially. To get
the whole bit field right aligned it is necessary to shift all pre-
ceding bytes right.
A read access to this register takes the top entry of the
receive FIFO. Both registers DGRTMA and DGRTMD are
overwritten by the next FIFO entry as result of a read access.
1
2
3
4
5
6
7
0
6
0
0
w
DGRTMA
r
0
x
7
1
0
1
0
LEN
2 1 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
x
Last byte of a field. The six right most bits
belong to the field.
A byte of a field. All bits belong to the field. At
least one byte follows.
Last byte of a field. Eight bits belong to the
field.
Impossible.
6
LEN usage, Receive and Transmit Length
DGRTMD Interpretation Examples
Rx Field & Tx More Address Register
x
5
Transmit More Address
Valid Bit Numbers
7 6 5 4 3 2 1 0
_ _ _ _ _ _ _ x
_ _ _ _ _ _ x x
_ _ _ _ _ x x x
_ _ _ _ x x x x
_ _ _ x x x x x
_ _ x x x x x x
_ x x x x x x x
x x x x x x x x
Receive Field
x
4
PRELIMINARY DATA SHEET
x
3
x
2
1
x
Micronas
x
0
Res