CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 195

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
Transmitted
Received
Corrected
Fig. 29–4:
RDL
r1:
r0:
This flag is set if the receive FIFO is full and the shift register
tries to store its contents to the FIFO because a new bit
arrives. In this case the FIFO is frozen but the shift register is
overwritten. It must be interpreted and cleared by the user. It
is cleared by reading an entry from the FIFO.
NEM
r1:
r0:
(see Fig. 29–5 on page 193)
NOF
r1:
r0:
It generates only an interrupt in the moment when the limit is
passed. It doesn’t generate interrupts when the FIFO is
empty (see Fig. 29–5 on page 193).
TGV
r1:
r0:
w0:
This flag will be set if there were received two consecutive T-
signs. It is reset by the HW if a non T-sign is received. It can
be cleared by the user if the related telegram is evaluated.
PV
r1:
r0:
w0:
It must be interpreted and cleared by the user. It is set when
the receive bit logic enters or leaves state passive high or
when it enters the state passive low.
Micronas
w
DGS0
r
RDL
x
x
7
PHASE = Start value of transmit counter.
NEM
Phase Correction
x
0
6
Telegram Valid
0
Receive Data Lost
Data lost
No data lost
Rx FIFO is Not Empty
There is at least one entry to read.
Empty.
Tx FIFO is Not Full
There is at least one entry free.
Full.
Telegram valid
Telegram not valid
Clear flag
Protocol Violation
Wake-up if bus is passive high.
Bus reset if bus is active.
No trouble
Clear flag
4
0
NOF
Status Register 0
x
1
5
16
16
16
TGV
0
4
Bit time
Phase delay
32
32
PV
32
0
3
ERR
48
48
0
2
48
x
x
1
0
0
0
June 12, 2003; 6251-579-1PD
ARB
0
0
Res
Fig. 29–5:
ERR
r1:
r0:
w0:
The HW sets this flag either if a dominant level is transmitted
and a recessive level is detected (collision error), or if there
was a wrong edge within a received bit. If a collision error is
detected during transmission, the flag ARB will be set too
and transmission stops immediately. This flag has to be
cleared by the user.
ARB
r1:
r0:
w0:
This flag will be set if a collision is detected during transmis-
sion. It must be cleared by the user. The transmit buffer was
flushed when ARB is true. It is impossible to write to the
transmit FIFO as long as ARB is true. Wait until flag TGV is
true before reloading TxFIFO. This is automatically done if
ARB is evaluated within the TGV interrupt subroutine only.
The Flags RDL, NEM, NOF, TGV, and PV trigger the inter-
rupt source signal (see Section 29.4.8. on page 197).
The first byte of an address field must be written to DGS1TA.
RxFIFO
NEM
Interrupt
TxFIFO
EMPTY
NOF
Interrupt
w
DGS1TA
r
0
7
STATE
Rx- and TxFIFO Timing
1
6
Error
Fatal error.
No error
Clear flag
Arbitration Lost
Arbitration lost.
No arbitration loss.
Clear flag
Status 1 & Tx Address Register
0
5
Transmit Address
0
4
CDC 32xxG-C
0
3
PW5 to 0
0
2
0
1
0
0
193
Res