CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 191

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
29. DIGITbus Master Module
The DIGITbus is a single line serial master-slave-bus that
allows clock recovery from the sign stream. The address and
data field are of arbitrary length.
The DIGITbus Master module is a HW-Module for connecting
a single chip controller to the DIGITbus. It generates the bus
clock and manages short telegrams autonomously. Trans-
mission and reception of long telegrams is supported by a
FIFO each. The DIGITbus Master may be used in a single or
in a multi master bus system.
Features
– Single master in a single master system.
– Clock master in a multi master system.
– Passive master in a multi master system.
29.1. Context
Apart from reset and clock line, the interface to the CPU con-
sists of registers connected to the internal address and data
bus. An output signal may be connected to the interrupt con-
troller.
A modified universal port builds the output logic which is con-
nected with its special input and output to the DIGITbus Mas-
Fig. 29–1:
Fig. 29–2:
Micronas
HW Option
HW Option
Interrupt
Interrupt
Reset
Reset
clock
clock
ADB
ADB
R/W
R/W
DB
DB
Context Diagram, Single Pin Bus
Context Diagram, Double Pin Bus
DIGITbus
DIGITbus
Master
Master
rx
tx
rx
tx
Universal Port with
Open Drain Output
Universal Port with
Push/Pull Output
Universal Port
SI
SO
SI
SO
June 12, 2003; 6251-579-1PD
Port Pins
Port Pin
– Bus clock generation.
– Receive and transmit a telegram with address and data
– Transmit FIFO and receive FIFO.
– Collision detection and arbitration.
– Abort transmission.
– Sleep mode.
– Bus monitor mode.
– Measure pulse width for phase correction.
– Phase correction.
– Receive wake-up and bus reset signal.
– Register interface to the CPU.
ter. This provides an easy way for the SW to hold the bus line
permanent low or high, or investigate bus level directly, with-
out support of DIGITbus Master HW.
An open drain output instead of a push/pull output is neces-
sary for the universal port to build a single line wired and bus.
External protection circuit
field.
1
MOSFET
e.g.
CDC 32xxG-C
+U
+U
Other
Transmitters
Other
Transmitters
DIGITbus
DIGITbus
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