CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 194

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

Table 29–1:
CDC 32xxG-C
29.3. Registers
The register mnemonic prefix “DG” stands for DIGITbus.
An “x” in a writable bit location means that this flag is
reserved. The user has to write a zero to this location for fur-
ther compatibility. An “x” in a readable bit location means that
this flag is reserved. A read from this location results in an
undefined value.
RUN
r/w1:
r/w0:
The module is absolute inactive if RUN is zero. Other flags
are not functional then.
GBC
r/w1:
r/w0:
ACT
r/w1:
r/w0:
Only the receive bit logic is active in low power mode.
RXO
r/w1:
r/w0:
192
r/w
Addr.
Offs.
0
1
2
3
4
5
6
7
DGC0
RUN
0
7
Mnem.
DGC0
DGC1
DGS0
DGRTMD
DGTL
DGS1TA
DGTD
DGRTMA
GBC
0
6
Run
Module clock is active.
Module is not clocked.
Generate Bus Clock
Module generates bus clock
No bus clock
Activate
Module is active (reception and transmission).
Module is sleeping (low power mode).
Receive External Only
Don’t receive own telegrams.
Receive all.
Register Mapping
ACT
Control Register 0
0
5
readable
RXO
0
4
Rx Length
reserved
Status 1
Rx Field
X
x
3
Tx Length
Control 0
Control 1
Status 0
0
2
PSC 2 to 0
writable
Tx More Addr.
Tx More Data
0
1
Tx Addr.
Tx Data
June 12, 2003; 6251-579-1PD
0
0
Res
PSC
r/w:
Table 29–2:
Note: With an input clock of 5 MHz, the bus clock frequency
of 31.25 kHz and its derivatives (16, 8, 4, 2, 1 kHz) can’t be
achieved. Thus, with a 5 MHz quartz the DIGITbus should be
operated in PLL mode.
INTE
r/w1:
r/w0:
ENEM
r/w1:
r/w0:
ENOF
r/w1:
r/w0:
PHASE
r/w:
The start of the transmit frame can be selected in increments
of 1/64 of a total bit time related to the rising edge. Values
between 0 and 15 are possible, but only the interval from 0 to
9 results in correct behavior.
Set PHASE to 2 if the DIGITbus is operated as clock master
(GBC = 1). This is necessary to compensate for internal
delay of 2 clocks. Refer to section 29.4.10. for further infor-
mation about phase correction.
r/w
PSC
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
DGC1
INTE
0
7
Divide
by
1
2
3
4
5
6
7
8
ENEM
0
6
Prescaler
Scaling value
Enable Interrupt
Enable interrupt
Disable interrupt
Enable Not Empty Interrupt
Enable
Disable
Enable Not Full Interrupt
Enable
Disable
Phase Correction Field
Transmit phase.
Clock Prescaler
ENOF
Control Register 1
Bus Clock in kHz
f
MHz
0
5
DB
= 4
31.25
x
x
4
62.5
20.8
15.6
12.5
10.4
PRELIMINARY DATA SHEET
8.9
7.8
0
3
f
MHz
DB
= 5
0
2
PHASE
78.1
39.1
26.0
19.5
15.6
13.0
11.2
9.8
0
1
f
MHz
DB
Micronas
= 10
0
0
156.25
31.25
78.1
52.1
39.1
26.0
22.3
19.5
Res