CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 92

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
11.2. Timing
Fig. 11–5:
The sample period of an incoming interrupt request lasts one
cycle in the worst case. It is sampled by an ISN with the fall-
ing edge of f
11.3. Registers
GE
r/w1:
r/w0:
Disabling happens as soon as nIRQ is inactive. An active
nIRQ will not be interrupted by writing a zero to GE.
TE
r/w1:
r/w0:
The Vector Table Logic doesn’t work if TE is disabled. Nei-
ther the correct ISR start address is returned nor the internal
signals IAck and IExit are generated on accessing the dedi-
cated memory location.
APRIO
r:
This field indicates the programmed priority of the actually
running ISR. It is modified by HW only.
90
f
(ECLK)
IntSrc
nIRQ
src#
SYS
r/w
r/w
CRI
AFP
GE
0
0
7
7
Timing
TE
0
0
SYS
6
6
Global Enable
Enable IRQ.
Disable IRQ.
Table Enable
Enable.
Disable.
Actual Priority
(Table 11–3)
APRIO
. Priority Encoder and comparator require
Control Register IRQ
Actual and Forced Priority Register
x
x
0
5
5
x
0
4
x
4
x
x
0
3
3
x
0
2
x
2
FPRIO
x
x
0
1
1
June 12, 2003; 6251-579-1PD
x
0
0
x
0
Res
Res
prio
another cycle. The CPU finally evaluates with the next falling
edge of f
This results in a maximum delay of 2 f
request to CPU input.
FPRIO
r/w:
Writing a value higher than the APRIO value to this location
raises the priority of the actual running ISR. It doesn’t
change APRIO. Only ISRs with a priority higher than the
forced priority are able to interrupt now.
It is necessary to first save the original FPRIO value before
raising the own priority by overwriting FPRIO. The saved
FPRIO value has to be restored before ISR exit.
This register shows the priority of the highest pending and
enabled interrupt source.
This register shows the number of the highest pending and
enabled interrupt source.
PEPRIO
PESRC
r
r
x
x
x
x
7
7
comp
SYS
.
x
x
x
x
6
6
Forced Priority
(Table 11–3)
CPU
Priority Encoder Priority output
Priority Encoder Source output
x
x
0
5
5
x
x
0
4
4
PRELIMINARY DATA SHEET
0
0
3
3
Source
0
0
2
2
Priority
SYS
0
0
1
1
cycles from
Micronas
0
0
0
0
Res
Res