CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 145

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
PRELIMINARY DATA SHEET
Start an SPI DMA sequence by writing to register SPIxD of
the corresponding SPI module. The data of this write may be
omitted. Then enable the DMA channel.
Start a Graphic Bus DMA sequence by reading from register
GD. The data of this read may be omitted. Then enable the
DMA channel.
22.3.5. External Triggered DMA Operation
The procedure is the same as with the self timed operation
with some distinctions.
In both cases (read/write) the SW initiates the first action in
the peripheral module. Enable the DMA channel after this
module has finished it’s work. Otherwise a DMA cycle may
happen to early transferring invalid data.
It is possible to do external triggered DMA transfers without
the SW initiating the first action. In this case the maximum
block size is limited to 255 byte because the count value in
the DMA vector has to be programmed with block size plus
one. In a write case (Fig. 22–7), the sequence starts with
data D1. In a read case (Fig. 22–8), the first DMA cycle
reads invalid data D0. The first element of the transferred
block has to be omitted in the latter case.
22.3.6. End of DMA Sequence
The end of the DMA sequence is indicated by the enable flag
(EN=0) and an interrupt which calls the ISR of the corre-
sponding I/O module.
The address field of the corresponding DMA vector points to
the next element after the last transferred element. The
counter field is at zero.
22.3.7. Enabling of a DMA Channel
Setting the flag EN to one enables the DMA channel. Make
sure that there is no pending DMA request at that point of
time. Clearing an active pending flag P and enabling the cor-
responding DMA channel must not be done with a single
instruction. This might lead to an unwanted DMA cycle. First
clear P and then set EN in two instructions.
22.3.8. Stall and Termination of a DMA Sequence
Clearing the flag DCxM.EN stalls a DMA sequence. Further
DMA requests of the disabled DMA channel set the pending
flag DCxM.P. Setting the flag DCxM.EN again enables the
DMA channel thus continuing the DMA sequence. This
mechanism has to be operated carefully because data may
be lost during a stall period.
A final termination of a DMA sequence can be achieved by
first disabling the DMA channel (DCxM.EN=0) and the
source of the DMA requests and secondly clearing the pend-
ing flag (DCxM.P=0). Don”t forget to clear DCxM.BYP if
furthter DMA requests shall generate an interrupt.
22.3.9. Disabling of the DMA Controller
First terminate all DMA channels (see 22.3.8.) and then clear
flag DST.DE. Don”t forget to clear DCxM.BYP if furthter DMA
requests shall generate an interrupt.
Micronas
143
June 12, 2003; 6251-579-1PD