CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 178

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
The ID contains the address of the telegram. 11 bits in the
standard mode or 29 bits in the extended mode.
ACC
r/w0:
r/w1:
Access determines the right of access for the CPU. The CPU
should not modify this flag after initialization. In operation
mode only the BI modifies it and the CPU reads it.
RSR
r/w0:
r/w1:
In the provide mode, RSR signals a send request from out-
side; in the fetch mode it means that a remote Tg is being
sent. It is set by the BI if a remote telegram has been
received. It is deleted as soon as the corresponding data
telegram has been transmitted.
EXF
r/w0:
r/w1:
In order to send/receive telegrams with extended address
format, this flag must be switched on. For standard telegrams
it is deleted.
DLC
r/w:
The DLC defines the number of data bytes transmitted. Only
telegrams with 0 to max. 8 data bytes are transmitted. If the
DLC of a TxTg contains a value >8, the entered DLC and
exactly 8 bytes will be transmitted. In the case of RxTgs the
received DLC, and therefore also values > 8 will be entered
by BI.
TIE
r/w0:
r/w1:
Masks the Tx interrupt for this com. object.
RIE
r/w0:
r/w1:
Masks the Rx interrupt for this com. object.
27.3. Application Notes
27.3.1. Initialization
After reset, a CAN Module is in standby mode (inactive).
Prior to entering active mode, proper SW configuration of the
U-Ports assigned to function as RX input and TX output has
to be made (Table 27–1). The RX port has to be configured
Special In and the TX port has to be configured Special Out.
Refer to “Ports” for details.
For entering active mode of a CAN, set the respective enable
bit (Table 27–1).
In the initialization phase, a configuration of the CAN node
takes place. The mode of operation of the BTL and the bus
coupling is set. The communication area is created in the
CAN-RAM. The different telegrams are specified in it.
The CAN node must be halted (HACK = TRUE) to carry out
the initialization. After a reset, the flags HLT and HACK are
set and initialization can take place. If initialization is required
on-line, the flag HLT must be set. However, the BI must ter-
176
Tx Interrupt Enable
Access
CPU does not have right of access.
CPU has right of access.
Remote Send Request
Remote telegram received.
Corresponding data transmitted.
Extended Format
Standard.
Extended.
Data Length Code
Data length.
Disable.
Enable.
Rx Interrupt Enable
Disable.
Enable.
June 12, 2003; 6251-579-1PD
SR
r0:
r/w1:
With SR, the microprocessor issues a send request. Both the
microprocessor and the BI write the SR flag. If the micropro-
cessor writes a one, the telegram is sent. The BI deletes the
SR flag after successful transmission.
TS
r/w0:
r/w1:
The TS flag is set by BI after a successful transfer and is
deleted by the microprocessor after a com. object has been
processed.
27.2.4.2. Data Field
The data field consists of 8 Byte. They are filled with tele-
gram data according to the DLC. Unused data bytes (DLC
less than 8) can be used by the user.
27.2.4.3. Time Stamp
TIMST
r:
The last two bytes in the CO are used for the time stamp.
At each SoF (Start of Frame) the free-running 16-bit counter
CANxCTIM is loaded into a register. When the Tg has been
correctly transmitted, this register is copied to the two time
stamp bytes of the corresponding CO.
Fig. 27–4:
minate any current transmission before it comes to a halt.
For the user this means that he must wait until HACK has
been set. If HLT is deleted after initialization, then BI begins
to participate in the bus traffic and to scan the CA for tasks.
During initialization, the error status register (CANxESTR)
and the interrupt index (CANxIDX) should be deleted, other-
wise no interrupts can be initiated. The error status mask
register default value after reset is not masked.
If telegrams with different identifiers are to be received in a
single CO, the identifier mask register must be initialized.
This defines which bit of the ID received must be the same
as the ID in the CO.
Bit timing registers 1, 2 and 3 and the output control registers
1 and 2 must be initialized in all cases.
The CA must be created in the CAN-RAM. The different COs
are created one after the other starting at the address 0. It is
important at this point that the three MSBs have been set in
the first byte after the last CO, i.e. at an address divisible by
14
15
Data 5
Data 6
Data 7
Time Stamp low
Time Stamp high
Time stamp
Send Request
Successful transmission.
Send request.
Transfer Status
Ready for Transfer.
Successful transfer.
Time Stamp
Counter value.
PRELIMINARY DATA SHEET
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