CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 162
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CDC3205G-C
Manufacturer Part Number
CDC3205G-C
Description
Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
Manufacturer
Micronas
Datasheet
1.CDC3205G-C.pdf
(260 pages)
- Current page: 162 of 260
- Download datasheet (3Mb)
CDC 32xxG-C
25.3. Registers
RBUSY
r0:
r1:
BRKD
r0:
r1:
FRER
r0:
r1:
OVRR
r0:
r1:
PAER
r0:
r1:
EMPTY
r0:
r1:
There is at least one entry present if EMPTY is zero. PAER,
FRER and BRKD are not valid if EMPTY is set.
FULL
r0:
r1:
TBUSY
r0:
r1:
Do not write to register UAxD as long as BUSY is true.
STPB
w0:
w1:
ODD
w0:
w1:
PAR
w0:
w1:
160
w
w
r
r RBUSY
UAxD
UAxC
x
0
x
x
7
7
BRKD
x
x
x
x
6
6
No error.
Overrun Detected
Overrun.
No error.
Receiver Busy
Not busy.
Busy.
Break Detected
No break.
Break.
Frame Error Detected
Error.
No overrun.
Parity Error Detected
Error.
Rx FIFO Empty
Not empty.
Empty.
Rx FIFO Full
Not full.
Full.
Transmitter Busy
Not busy.
Busy.
Stop Bits
One stop bit.
Two stop bits.
Odd Parity
Even parity.
Odd parity.
Parity On
No parity.
Parity on.
FRER
UART x Data Register
x
UART x Control and Status Register
x
x
x
5
5
Transmit register
Receive register
OVRR
x
0
x
x
4
4
PAER
STPB
x
x
0
3
3
EMPTY
ODD
x
1
0
2
2
FULL
PAR
0
0
x
1
1
TBUSY
June 12, 2003; 6251-579-1PD
LEN
x
0
0
0
0
Res
Res
Res
LEN
w0:
w1:
Table 25–3:
The Baud Rate Registers UAxBR0 and UAxBR1 have to be
written low byte first to avoid inconsistencies. UAxBR0 is the
low byte.
Valid entries in the Baud Rate Registers range from 1 to
8191. Don’t operate the baud rate generator with its reset
value zero.
w
LEN
0
0
0
0
1
1
1
1
w
w
UAxBR0
UAxBR1
UAxCA
x
-
0
0
7
7
7
PAR
0
0
1
1
0
0
1
1
x
-
0
0
6
6
6
Length of Frame
7bit frame.
8bit frame.
Telegram Format and Length
UART x Baud Rate Register low byte
UART x Baud Rate Register high byte
x
UART x Compare Address Register
-
0
0
5
5
5
STPB
0
1
0
1
0
1
0
1
Bit 7 to 0 of Baud Rate
Bit 7 to 0 of address
0
0
0
4
4
4
PRELIMINARY DATA SHEET
Bit 12 to 8 of Baud Rate
Format
S, 7D, T0
S, 7D, T0, T1
S, 7D, P, T0
S, 7D, P, T0, T1
S, 8D, T0
S, 8D, T0, T1
S, 8D, P, T0
S, 8D, P, T0, T1
0
0
0
3
3
3
0
0
0
2
2
2
0
0
0
1
1
1
Micronas
0
0
0
0
0
0
L
9
10
10
11
10
11
11
12
TG
Res
Res
Res
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