CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 65

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
Fig. 6–4:
6.5.2.4. Forced Hardware Reset
Setting flag CSW0.FHR immediately forces the RESETQ pin
low. This allows the SW to restart the whole system by HW
reset.
6.5.2.5. Wake-Up Reset
Entering one of the power saving modes sets the corre-
sponding flag in register CSW1, but does not pull RESETQ
low. However, wake-up from one of the power saving modes
(signal WAKE_RES_5 in Fig. 6–3) does pull RESETQ low.
6.5.3. External Reset Sources
As long as the Reset Comparator on the pin RESETQ
detects the low level, the overall IC is reset except the PSM/
RTC. On this pin, external reset sources may be wire-ored
with the IC internal reset sources, leading to a system wide
reset signal combining all system reset sources.
Micronas
reset in
2nd write
& even
power on
res CSW1
1st write
2nd write & even
3rd write & odd
Watchdog Block Diagram
S Q
R
Trigger Reg1
8
CSW1
=
1
3rd write
& odd
&
D
C
S
June 12, 2003; 6251-579-1PD
Trigger Reg2
Q
8
CSW1
&
1st write
6.5.4. Summary of Module Reset States
After reset the IC modules are set to the reset state (Table 6–
4)
Table 6–4: Status after Reset
Module
CPU
Interrupt
Controller
U-Ports
High current
ports
LCD module
Watchdog
Clock monitor
SRAM, CAN-
RAM
PSM
1st write
1
load
Timer Register
Status
CPU Fast mode (f
Interrupts are disabled. Priority regis-
ters, request flip flops and stack are
cleared.
Normal mode. Output is tristate.
Normal mode. Output is low.
Registers are reset. No display.
Inactive after POR and Wake-up. SW
may activate. Unaffected in the other
cases.
Active. SW may deactivate.
When power was off, content is unde-
fined. When power was not removed,
last state is contained.
When power was off, content is unde-
fined, except registers WSC, OSC, POL
and SMX. When power was not
removed, only registers OSC (flags RC,
XK,XM), POL and SMX are reset.
8-Bit-Counter
&
8
CSW1
CDC 32xxG-C
clk
S Q
R
PLL,FAST: f
SLOW: f
OSC
zero
).
15
CSW1.WDRES
/128
15
WDRES
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