CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 160

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
During reception, the following checks are performed accord-
ing to the register UAxC setting:
1. A parity error is detected if the parity of the received tele-
gram does not match the programmed parity. The flag PAER
in register UAxC is set in this case. Differing telegram length
settings in register UAxC and receiver may also cause parity
errors.
2. A frame error is detected if the level of start or stop bits
violate the transmission rule. The flag FRER in register
UAxC is set in this case.
3. A break condition is detected if the receive input remains
low for one complete telegram duration. When a break starts
during telegram, this condition must extend over another
telegram length to be properly detected. This event sets the
flag BRKD in register UAxC and can trigger the interrupt
source output if enabled. After a break, the receive input
must be high for at least 1/4 of the bit length before a new
telegram can be received.
Telegrams of an external RS232 interface are correctly
received, even if they are transmitted without gaps (the start
bit immediately follows the stop bit of the preceding tele-
gram).
25.1.4.3. Receive FIFO
The receive FIFO is able to buffer the data fields of two con-
secutive telegrams. But not only the data field of a telegram
is double buffered, the related information is double buffered
25.2. Timing
The duration of a telegram results from the total telegram
length in bits (L
baud rate (BR).
The incoming signal is sampled with the sample frequency
and filtered by a 2 of 3 majority filter. A falling edge at the out-
put of the majority filter starts the receive timing frame for the
telegram. An individual bit is sampled with the fifth sample
clock pulse within that timing frame (cf. Fig. 25–4 and 25–5).
If a bit was the last bit of its telegram, reception of a new tele-
gram can start immediately after this sample. With a receive
telegram, interrupt source is triggered and flags are set just
after the sample of the last stop bit. With a transmit telegram,
interrupt source is triggered and BUSY reset after the nomi-
nal end of the last stop bit.
158
TG
) (see Table 25–3 on page 160) and the
t
TG
=
L
--------- -
BR
TG
June 12, 2003; 6251-579-1PD
too. The flags PAER, FRER and BRKD in register UAxC
apply to a certain telegram and are thus double buffered.
The receive FIFO is full if two telegrams were received but
the SW did not yet read register UAxD. If there is a third tele-
gram, it is not written to the FIFO and its data are lost. The
flags EMPTY, FULL and OVRR show the status of the FIFO.
EMPTY indicates that there is no entry in the FIFO. FULL will
be set with the second entry in the receive FIFO and indi-
cates that there is no more entry free. OVRR indicates that
there was a third telegram which could not be written to the
FIFO.
Status flags are readable as long as the corresponding data
field was not read from register UAxD. As soon as a FIFO
entry is read out, the status flags of this entry are lost. They
are overwritten by the flags of the second entry. SW first has
to read the flags and then the corresponding FIFO entry.
The flags PAER, FRER and BRKD apply to a certain tele-
gram and are only valid if there is at least one entry in the
FIFO (EMPTY = 0). The flags EMPTY, FULL and OVRR
apply to the FIFO and are valid all the time.
25.1.5. Inactivation
Returning a UART module to standby mode by resetting its
respective enable bit (Table 25–1) will immediately terminate
any running receive or transmit operation and will reset all
internal registers.
PRELIMINARY DATA SHEET
Micronas