CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 41

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
The RTC allows the CPU to select from one-second to one-
day clocks (see section ‘Power Saving Module’ for details)
as wake signal. Beside serving as wake source, the CPU
may use the RTC as real time clock that is not halted by
resets.
A Polling Module, driven by a selectable RTC clock, may be
configured to generate a polling pulse on H0.2 and sample
the Wake Ports immediately after. Thus a periodical polling
of Wake Ports may be achieved, with no continuous power
consumption in external circuitry.
To prepare for STANDBY mode, the CPU has to configure
the desired RTC wake clock (see chapter “Power Saving
Module”, section “RTC Module”), beside the desired Wake
Port(s), see chapter “Power Saving Module”, section “Port
Wake Module”.
To enter STANDBY mode, the CPU selects WAKE/STBY in
register SR1.CPUM.
The device will immediately enter STANDBY mode by reset-
ting all circuitry, stopping the unused clocks, and powering
down all regulators and remaining analog circuitry. As long
as all Wake Port inputs are kept at CMOS input levels
(V
only amount to the requirement of the oscillator(s) and the
slow-clocked RTC and Polling Modules.
To exit STANDBY mode, the previously configured Wake
source has to switch. Immediately a Wake Reset sequence
will be started internally that pulls the RESETQ pin low and
releases it as soon as all internal reset sources have become
inactive. See chapter “Core Logic” for details on internal
reset sources. After reset, the CPU starts in FAST mode, as
usual.
4.2.2.3. IDLE Mode
IDLE mode allows usage of the same wake sources as
STANDBY mode. But in contrast to WAKE and STANDBY
4.3. Clock System
The IC contains a quartz oscillator circuit that only requires
external connection of a quartz and of 2 oscillation capaci-
tors. Its start-up and run properties are controllable by SW.
See section “Core Logic” for details.
The oscillator clock f
the various modules with its specific clock (Fig. 4–2).
A frequency multiplying PLL allows to select the system
clock f
module operation.
A divider chain divides f
clocks f
some cases, hardware or HW option defined in other cases.
The module descriptions give details.
The standby register field SR1.CPUM selects the operating
mode (Table 4–3).
Micronas
il
=xV
SYS
SS
0
to f
0.3V and V
to be higher than f
17
. Module clock selection is software defined in
XTAL
ih
=xV
IO
drives a clock system that supplies
down to supply peripheral module
DD
XTAL
0.3V), the supply currents will
for high speed CPU and
June 12, 2003; 6251-579-1PD
modes, an auxiliary V
core functionality (Table 4–2):
– the internal SRAM and CAN-RAM keeps its programmed
– all U-, P- and H-Port registers (see chapter “Ports”) keep
Leakage currents in these additionally powered modules add
to the device current consumption.
To prepare for IDLE mode, the CPU has to configure the
desired RTC wake clock (see chapter “Power Saving Mod-
ule”, section “RTC Module”), the desired Wake Port(s) (see
chapter “Power Saving Module”, section “Port Wake Mod-
ule”) and the port registers as desired.
To enter IDLE mode, the CPU selects IDLE in register
SR1.CPUM.
The device will immediately enter IDLE mode by resetting all
circuitry except the port registers, stopping the unused
clocks, and powering down all main regulators and remain-
ing analog circuitry, but not the auxiliary V
long as all U-, P- and H-Ports, that are configured as inputs,
are kept at CMOS input levels (V
V
requirement of the oscillator(s), the RTC and Polling mod-
ules and mere leakage currents flowing mainly in SRAM.
To exit IDLE mode, the previously configured Wake source
has to switch. Immediately a Wake Reset sequence will be
started internally that pulls the RESETQ pin low and
releases it as soon as all internal reset sources have become
inactive, but port registers and SRAM will be exempted from
being reset. See chapter “Core Logic” for details on internal
reset sources. After reset, the CPU starts in FAST mode, as
usual.
ih
data
their programmed state.
=xV
DD
0.3V), the supply currents will amount to the
DD
regulator allows to maintain some
CDC 32xxG-C
il
=xV
DD
SS
regulator. As
0.3V and
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