CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 94

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
11.4. Principle of Operation
11.4.1. Reset
Clearing standby register flag SR1.IRQ resets the ICU (see
Fig. 11–4 on page 88). The registers are reset to their men-
tioned values (see Section 11.3. on page 90) and cannot be
modified. The nIRQ output is inactive and the actual priority
level logic is cleared.
11.4.2. Initialization
Proper configuration of the interrupt sources in the peripheral
modules has to be made prior to initialization of the ICU.
Initialization is possible after the standby register flag
SR1.IRQ has been written to one. Now the registers can be
modified by SW. But no interrupt request is generated to the
CPU.
Install the vector table beginning at an even page address (9
LSB are zero). Each entry has to be a 32 bit start address of
an interrupt service routine. The vector table has to be
located near ( 4kB) the load PC instruction. Write the start
address of the vector table to the Vector Table Base register
VTB. Further access to register VTB is not necessary until
you want to switch to another vector table at another location.
Set up the Interrupt Source Node registers ISNx with the
necessary priority and enable them. The pending flags have
to be cleared, because they are not cleared by SR1.IRQ and
are operative all the time. Clearing an active pending flag
and enabling the corresponding ISN must not be done with a
single instruction. This might lead to an unwanted (spurious)
interrupt which is directed to the default vector. First clear P
and then set E in two instructions. Interrupt sources which
shall not generate interrupts must not be enabled and need
no priority (PRIO=0), but can be operated by polling and
resetting the pending flag P by SW.
11.4.3. Operation
The ICU is operable in all CPU modes. However, interrupts
have to be disabled during CPU mode switching to prevent
undefined clock system behavior.
Setting both flags CRI.GE and CRI.TE enables the ICU at
last. When an interrupt occurs, execution starts at address
0x18. For proper operation of the ICU the jump to the inter-
rupt service routine has to be done by the PC relative load
PC instruction
LDR PC,[PC,#<12_bit_offset>],
where the operand [PC,#<12_bit_offset>] must point to the
first entry of the vector table. Due to the 12_bit_offset the
11.5. Application Hints
11.5.1. Hardware Triggered Interrupts
Normally the connected peripheral modules are setting the
pending flag P. If the ISN is enabled (E=1) and the priority is
not zero, an IRQ is generated. The P flag will be reset as
soon as the corresponding interrupt service routine is called.
It is not required and should be avoided to modify the P flag
of those ISNs by SW.
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June 12, 2003; 6251-579-1PD
vector table has to be located within 4kB from the above
instruction. Above instruction is called vectoring. There are
two possibilities for the point of time, direct and delayed,
when vectoring takes place.
11.4.3.1. Direct Vectoring
Above instruction is the first instruction which is executed
when an interrupt occurs. The address 0x18 contains the PC
relative load PC instruction.
11.4.3.2. Delayed Vectoring
Above instruction is delayed. The address 0x18 contains a
jump to a short piece of code which does all what has to be
done for every ISR (Save LR, SPSR and working registers).
After this common prefix the jump to the appropriate ISR is
launched by the PC relative load PC instruction.
11.4.4. CPU Mode Switching
A CPU mode switch (see Section 4.2. on page 35) has to be
handled like critical code. Disable the ICU prior to the mode
switch by setting CPSR flag I of the ARM core (see Section
11.5.7.1. on page 93) or by clearing flag CRI.GE (see Sec-
tion 11.5.7.2. on page 94). The ICU can be enabled again
after the CPU mode switch sequence has finished. If the
mode switch has to be done within an ISR, wait with the gen-
eration of the signal IExit until the ICU has been enabled
again.
11.4.5. Inactivation
An interrupt source can be disabled locally by clearing the
enable flag E in the corresponding ISN register. Even a
pending interrupt can be disabled this way. A disabled ISN
does not participate in sending interrupt requests to the
CPU.
All interrupt sources can be disabled globally by clearing the
global enable flag CRI.GE. It is impossible to inactivate an
active nIRQ output signal by clearing CRI.GE. An active
nIRQ will be served and only further IRQs can be sup-
pressed by setting the GE flag.
The pending flag P stays operative in both cases and may be
polled by SW.
A zero in the standby register flag SR1.IRQ immediately
resets registers and logic and forces the nIRQ output to inac-
tive.
11.5.2. Software Triggered Interrupts
Any ISN which is not used by the connected peripheral mod-
ule can be used for generating IRQ interrupts by SW. It must
be avoided that the interrupt source of this ISN is also gener-
ating interrupt requests. Either the corresponding peripheral
module has to be switched off or its interrupt source output
has to be disabled.
PRELIMINARY DATA SHEET
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