CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 175

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
w1:
Is set by the BI when the CRC received does not coincide
with the CRC calculated. The user must delete it.
FRM
r0:
r1:
w0:
w1:
Is set by the BI when an incorrect bit is received in a field with
specified bit level (start of frame, end of frame, ...). The user
must delete it.
ACK
r0:
r1:
w0:
w1:
Is set by the BI when there is no acknowledge for a transmit-
ted Tg. The user must delete it.
The interrupt index indicates the source of the interrupt. If a
transmission has been the cause of an interrupt, the interrupt
index points to the corresponding telegram descriptor
(CANxIDX = 0..253). If an error has been responsible for the
interrupt, the interrupt index designates the error status reg-
ister (CANxIDX = 254). After dealing with the interrupt, the
user must eliminate the cause of the interrupt and set the
interrupt index to minus one (255 = EMPTY). As soon as
CANxIDX is empty, the BI can enter a new index and initiate
an interrupt. An interrupt can only be initiated when CANx-
IDX contains the value 255.
r/w0:
r/w1:
The identifier mask register is 29 bits long; the MSB is in the
MSB position in the lowest byte address. The CANxIDM
defines a mask for the acceptance of address groups. Only
the permitted bits are used for comparison with a received
identifier. Whether the mask is used can be determined indi-
vidually for each receive object.
Micronas
r/w
r/w
r/w
r/w
r/w
CANxIDX
CANxIDM
1
0
7
7
Identifier Mask Bits 4 to 0
0
1
6
6
Form Error
No form error.
Form error.
Clear.
Unaffected.
Clear.
Acknowledge Error
No acknowledge error.
Acknowledge error.
Unaffected.
Clear.
Don’t care.
Compare.
Interrupt Index Register
Identifier Mask Register
Identifier Mask Bits 20 to 13
Identifier Mask Bits 28 to 21
0
1
5
5
Identifier Mask Bits 12 to 5
Interrupt Index
0
1
4
4
0
1
3
3
x
0
1
2
2
x
0
1
1
1
June 12, 2003; 6251-579-1PD
x
0
1
0
0
3
2
1
0
Res
Res
MSAM
r/w0:
r/w1:
SYN
r/w0:
r/w1:
BPR
r/w:
The baud rate pre-scaler sets the length of a time quantum
for the bit timing logic.
t
With the 6-bit counter it is possible to extend t
1...64. Values from 0 to 63 are allowed.
0: t
1: t
2: t
3: t
TSEG2
r/i:
TSEG2 determines the number of time quanta after the sam-
ple point. Permitted entries: 1...7 (result in 2...8 TQ).
TSEG1
r/i:
TSEG1 determines the number of time quanta before the
sample point. Permitted entries: 2...15 (result in 3...16 TQ).
SJW
r/i:
SJW defines by how many TQs a bit may be lengthened or
shortened because of resynchronization. Permitted entries:
1...4 (result in 1...4 TQ). Values greater than 4 must not be
used.
Q
r/w
r/w
r/w
CANxBT1
CANxBT2
CANxBT3
= (BPR + 1) / f
Q
Q
Q
Q
MSAM
= 1 / f
= 2 / f
= 3 / f
= 4 / f
rsvd
rsvd
0
0
x
7
7
7
0
0
0
0
rsvd
SYN
0
0
x
6
6
6
Multi Sample
Bus level is determined only once per bit.
Bus level is determined three times per bit.
Sync On
Synchronization with falling edges only.
Synchronization with rising edges too.
Baud Rate Pre-scaler
Pre-scaler value.
Time Segment 2
TSEG2 value.
Time Segment 1
TSEG1 value.
Synchronization Jump Width
SJW value.
0
TSEG2
.
rsvd
etc.
Bit Timing Register 1
Bit Timing Register 2
Bit Timing Register 3
0
0
x
5
5
5
rsvd
0
0
x
4
4
4
CDC 32xxG-C
rsvd
0
0
x
3
3
3
BPR
0
0
0
2
2
2
TSEG1
SJW
Q
0
0
0
1
1
1
by a factor of
0
0
0
0
0
0
173
Res
Res
Res