CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 19

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
LCD module is configured as slave and the external LCD
driver operates as master.
LCD-CLK-OUT
The Clock output of the LCD module provides a clock signal
to optional external LCD slave drivers if the internal LCD
module is configured as master and the other LCD drivers
are slaves.
LCD-SYNC-IN
The Synchronization input of the LCD module receives the
sync signal from an optional external LCD master driver. This
input is active if the internal LCD module is configured as
slave and the external LCD driver serves as master.
LCD-SYNC-OUT
The Synchronization output of the LCD module provides a
sync signal to optional external LCD slave drivers if the inter-
nal LCD module is configured as master and the other LCD
drivers are slaves.
LCK
This output signal indicates that the PLL has locked.
LOCK (ARM) 1)
This is the LOCK output signal of the ARM indicating that the
processor is performing a “locked” memory access when
high.
MAS0, MAS1 (ARM) 1) 2)
These are ARM output signals used by the processor to indi-
cate to the external memory system when a word transfer or
a half-word or a byte length is required.
MTI
This is a test input line. It is intended for factory test only. The
application should not use this signal.
MTO
This is a test output line. It is intended for factory test only.
The application should not use this signal.
nEXEC (ARM) 1)
This is the “Not executed” signal of the ARM indicating that
the instruction in the execution unit is not being executed
when high.
nM0 to nM4 (ARM) 1)
These pins output the “Not processor mode” signal of the
ARM.
nMREQ (ARM) 1) 2)
This pin outputs the “Not memory request” signal of the
ARM. The processor requires memory access during the fol-
lowing cycle when low.
nOPC (ARM) 1)
This pin outputs the “Not op-code fetch” signal of the ARM.
The processor is fetching an instruction from memory when
low.
nRESET (ARM)
This pin outputs the “Not reset” signal of the ARM. This pin is
not an input.
nRW (ARM) 1)
This pin outputs the “Not read/write” signal of the ARM. High
indicates a processor write cycle, low a read cycle.
nTRANS (ARM) 1)
This pin outputs the “Not memory translate” signal of the
ARM. When low it indicates that the processor is in user
mode.
Micronas
June 12, 2003; 6251-579-1PD
nTRST (ARM)
This pin is the “Not test reset” signal of the ARM. It resets the
boundary scan logic of the CPU when low. It is also the reset
for the Emulation JTAG interface (not for the application
JTAG interface).
nWAIT (ARM) 1) 2)
This pin outputs the “Not wait” signal of the ARM. It is not
possible to cause a wait via this pin.
OEQ 4)
The Output Enable signal connects to the OEQ pin of exter-
nal memory for read access. Active LOW.
P0.0 to P0.7, P1.0 to 1.7 and P2.0 to P2.1
P0.0 to P1.7 are 16 analog ports that are the multiplexed
input channels of the ADC. All analog ports P0.0 to P2.1 can
also be used as digital input lines. The analog ports P1.2 to
P1.7 can also be used as port interrupts.
P06COMP
Analog port P0.6 is additionally input to the P06 Comparator.
PFM0, 1
These are the outputs of the PFM0 and PFM1 Pulse Fre-
quency Modulators.
PINT0 to PINT5
The Port Interrupt 0 to 5 inputs serves as inputs to the inter-
rupt controller via the port interrupt module. HW option
PM.PINT has to be set to determine which of the possible
input pins are used as source of PINT0 to 5.
PIPESTAT0 to PIPESTAT2 (ETM) 2)
These signals indicate the pipeline status of the ETM.
POL
Output of the Polling Module.
PWM0 to PWM11
These are the outputs of the PWM module. Some of these
PWM signals are directed to two pins.
RANGEOUT0, RANGEOUT1 (ARM) 1)
These pins output the “ICEBreaker rangeout” signals of the
ARM. They indicate that ICEBreaker watch point register 0
or 1 has matched the conditions currently present on the
address, data and control busses.
RESETQ
This bidirectional signal is used to initialize all modules and
start program execution.
Two comparators distinguish three input levels:
– A low level resets all internal modules.
– A medium level activates all internal modules and starts
program execution. An alarm signal is generated which can
be directed to the interrupt controller.
– A high level keeps all internal modules active and cancels
the alarm signal.
The RESETQ input signal must be held low for at least two
clock cycles after VDD reaches operating voltage.
Internal reset sources output their reset request on the
RESETQ pin via an internal open drain pull-down transistor.
Thus RESETQ can be wire-ored with external reset sources.
The internally limited pull-down current allows direct connec-
tion to large capacitors. The connection of such a capacitor
(e.g. 10nF) is recommended to reduce the capacitive influ-
ence of the neighboring XTAL2 pin.
CDC 32xxG-C
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