CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 93

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
The register VTB has to be programmed with the memory
base address of the interrupt vector table. The interrupt vec-
tor table has to start at an even page address (9 LSB are
zero) and is not longer than one page (256 bytes). Besides
the start address of the interrupt vector table VTB defines
two addresses which perform HW actions when accessed
and CRI.TE is set.
Every word read access to the location addressed by VTB
deactivates the nIRQ output. If the comparator output is
active, the internal signal IAck is activated, which returns the
ISR start address of the ISN with the highest active priority,
clears the corresponding P flag and saves the interrupted pri-
ority.
Every word write access to the location addressed by VTB
plus 0x100 activates the internal signal IExit.
Accessing these locations ([VTB] and [VTB]+0x100) without
generating IAck or IExit is possible when the Vector Table
Logic is disabled (CRI.TE = 0).
M
w1:
r/w0:
This flag is modified by SW only and always reads as 0. It
allows modification of register ISNx without influence to flag
P. Without this flag a HW modification of flag P could be cor-
rupted by a simultaneous read-modify-write of register ISNx.
P
r/w1:
r/w0:
This flag can be modified by HW and SW. It is set by HW
when the corresponding interrupt source input is activated. If
Micronas
r/w
r/w
r/w
r/w
r/w
VTB
ISNx
M
0
0
0
7
7
0
0
P
x
6
6
Modify Pending Flag (Table 11–2)
Modify Pending flag.
Don’t modify Pending flag.
Pending (Table 11–2)
Interrupt is pending.
No interrupt pending.
Vector Table Base
Interrupt Source Node Register x
0
Address bit 15 to 9
0
E
0
5
5
Address bit 23 to 16
0x00000000
0
0
x
4
4
x
0
0
0
3
3
0
0
0
2
2
PRIO
0
0
0
1
1
June 12, 2003; 6251-579-1PD
0
0
0
0
0
0
3
2
1
0
Res
Res
Offs
this interrupt source node is enabled, this flag is cleared by
HW as soon as the corresponding ISR is called.
Table 11–2:
E
r/w1:
r/w0:
This flag is modified by SW only.
PRIO
This field is modified by SW only (Table 11–3).
Table 11–3:
M
0
0
1
1
PRIO
3
0
0
0
:
1
1
P
0
1
0
1
2
0
0
0
:
1
1
Read
Not pending
Pending
Not possible
1
0
0
1
:
1
1
Enable
Enable interrupt.
Disable interrupt.
Interrupt Source Node Priority
Pending Flag Access
Priority Encoding
0
0
1
0
:
0
1
Priority number
0 (No priority)
1 (Lowest priority)
2
:
14
15 (Highest priority)
CDC 32xxG-C
Write
Don’t modify P
Clear P
Set P
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