CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 198

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
Table 29–6:
29.4.3.2. Receiver/Transmitter
Setting the flag ACT activates the receive and transmit logic.
From now on all telegrams are received in the receive FIFO.
Writing to the transmit FIFO initiates transmission of a tele-
gram.
The bus clock (T-signs) must be activated some time before
the first telegram is transmitted. This is necessary, because
other modules may use a PLL for generating the internal
clock from the bus clock. No telegram shall be transmitted
before all modules have locked on the bus clock.
29.4.3.3. Single Master System
In a single master system (no collision possible), you can
suppress reception of transmitted telegrams by setting flag
RXO (receive external only). This unburdens the CPU from
clearing the receive FIFO of those telegrams.
29.4.3.4. Multi Master System
In a multi master system it is necessary that each transmitted
telegram is received too, because arbitration may be lost and
then the transmitter becomes a receiver. If arbitration was
not lost, the receive FIFO must be read to empty it. The flag
RXO has to be cleared in a multi master system.
29.4.4. Transmission
Transmission is initiated by writing a telegram into the trans-
mit FIFO.
If the field length is not a multiple of 8 bit, the total field length
modulo 8 has to be written to register DGTL. This must be
done once for each field and before any entry to registers
DGS1TA, DGTD, DGRTMA or DGRTMD. If the total field
length is a multiple of 8 it is not necessary to write the field
length to register DGTL.
The first entry of a field (address or data) has to be written
right aligned to register DGS1TA (address) or DGTD (data).
Further entries of the same field, if it is longer than 8 bit, have
to be written to DGRTMA (more address) or DGRTMD (more
data). A telegram is transmitted MSB first, hence fields have
to be written to transmit FIFO MSB first.
196
Mod-
ule
Name
DIGIT-
bus
HW Options
Item
Clock
Input
Module specific settings
Address
DC
PM.CACO DIGIT-
Initialization
Item
DIGIT-
OUT
IN
Setting
U2.6 spe-
cial out,
double
pull-down
mode (sin-
gle pin
bus) or
special out
(double pin
bus)
U2.4 (spe-
cial in) or
U2.6 (spe-
cial out)
June 12, 2003; 6251-579-1PD
Enable
Bit
SR0.
DGB
Table 29–7:
A new address field is transmitted if there were at least 4
consecutive T-signs on the bus. A new data field is transmit-
ted if there was exactly one T-sign. If the last bit of a field was
transmitted and there are no more entries in the transmit
FIFO, the transmitter stops sending. After reception of two
consecutive T-signs the telegram valid flag TGV is set. This is
the signal for the SW to evaluate whether transmission was
correct or whether an arbitration loss or an error canceled
transmission (flags ARB, PV and ERR). In the latter case SW
must initiate retransmission.
A telegram has been transmitted correctly, if ARB and ERR
are false and EMPTY is true.
Transmission starts with the first entry in the transmit FIFO.
Consecutive fields should be entered before the transmission
of the preceding field is finished. Take care about possible
interrupts.
29.4.4.1. Transmit FIFO
SW must ascertain that there is an empty entry in the trans-
mit FIFO before writing to it. Flag NOF (not full) indicates that
there is at least one entry free. Flag EMPTY indicates com-
plete emptiness of transmit FIFO. After reset, FLUSH or ARB
wait until flag TGV is true before rewriting TxFIFO.
Short telegrams can completely be buffered in the FIFO.
Managing long telegrams is a SW job. The SW must buffer
long telegrams and write the parts in time. The transmit FIFO
is intended to unburden the CPU from immediately reaction
on an NOF interrupt. If an entry becomes free, the SW has
time to write, as long as it needs to transmit two FIFO entries
and the contents of the transmit shift register. This time must
not necessary be the duration for sending 24 bit. May be only
one bit of each remaining FIFO entry has to be send.
The transmit FIFO is not intended for telegram tracking. Only
one transmit telegram at a time shall be entered.
29.4.5. Reception
Every non T sign is shifted into the receive shift register. If it
is full or if a T sign was received, the shift register is stored
into the receive FIFO. This is done until the receive FIFO is
RUN
0
1
1
1
1
1
1
GBC
x
0
1
0
x
x
x
Operating modes
ACT
x
x
x
0
1
1
1
PRELIMINARY DATA SHEET
RXO
x
x
x
x
x
0
1
Remarks
Standby mode
Passive master. Exter-
nal bus clock genera-
tion is necessary.
Clock master
Sleep mode
Active mode
Receive all. (Recom-
mended in multi master
system)
Receive external only.
(Recommended in sin-
gle master system)
Micronas