CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 173

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
27.2.3. Global Control and Status Registers (GCS)
The GCS registers can be used to determine the behavior of
the CAN interface. As well as flags for the interrupts, halt and
sleep modes, they also contain interrupt index, ID mask, bus
Fig. 27–2:
Access modes:
r:
w:
i:
w0:
w1:
HLT
r/w0:
r/w1:
Switches the CAN interface into the halt mode. Transmis-
sions which have been started are brought to an end. The
Micronas
r/w
15
16
17
CANxCTR
0
Global Control and Status
HLT
Control
Status
Error Status
Interrupt Index
ID Mask 28 ... 21
ID Mask 20 ... 13
ID Mask 12 ... 5
ID Mask 4 ... 0
Bit Timing 1
Bit Timing 2
Bit Timing 3
Input Control
Output Control
Transmit Error Counter
Receive Error Counter
Error Status Mask
Capture Timer low
Capture Timer high
1
read
write
init (BI halted)
clear
set
7
SLP
Memory allocation
0
6
Halt
Run.
Halt.
GRSC
Control Register
0
5
EIE
0
4
GRIE
0
3
ESTR
CTIM
OCR
REC
ESM
CTR
STR
TEC
IDM
BT1
BT2
BT3
ICR
IDX
GTIE
0
2
BOST
0
1
June 12, 2003; 6251-579-1PD
rsvd
0
x
(n+1)*16
n*16+15
Res
n*16
15
16
31
32
47
0
1
2
Communication Area
Control
ID 28 ... 21
ID 20 ...13
ID 12 ... 5
ID 4 ... 0 and Control
DLC and Control
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Time Stamp low
Time Stamp high
TD
Data and Time Stamp
TD
Data and Time Stamp
TD
Data and Time Stamp
Control: CM = 7
timing, error status, output control registers, baud rate pre-
scalers, Tx and Rx error counters as well as the capture
timer.
halt acknowledge is indicated in the status register (HACK).
Re-initialization can be carried out in the halt mode (HACK is
set). After this, the halt flag must be deleted again. After a
reset, HLT is set.
If HLT is set during a Tx-Tg and this has to be repeated (error
or no acknowledge), the BI stops yet. The corresponding
TxCO is still reserved, however, and can no longer be oper-
ated from BI. Therefore, when HLT is set, the CA should
always be re-initialized if the last Tx-Tg has not been cor-
rectly transmitted (Status Transfer Flag is still deleted).
If HLT is set during the BI is in Bus-Off mode, the BI stops
after Bus-Off mode is finished. Flag BOFF is cleared then
and receive and transmit error counters are reset to zero.
SLP
r/w0:
r/w1:
The BI goes into the sleep mode when the sleep flag is set
and a started Tg is terminated. The sleep mode is finished
Sleep
Run.
Sleep.
Com.-Obj. 2
Com.-Obj. 3
Com.-Obj. n
End of Com. Area
Com.-Obj. 1
Telegram
Descriptor
TD
CDC 32xxG-C
171