CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 166

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
26.1. Principle of Operation
26.1.1. General
26.1.2. Hardware Settings
Since the telegram clock rate is register programable there is
no HW option for the I
26.1.3. Initialization
After system reset the I
internal clock is halted and all registers are set to their reset
Table 26–1:
26.1.4. Operation
A complete telegram is assembled by the software out of
individual sections. Each section contains 8-bit data. This
data is written into one of the six possible write registers.
Depending on the chosen address, a certain part of an
I
acknowledge. By means of corresponding calling sequences
it is therefore possible to join even very long telegrams (e.g.
long data files for auto increment addressing of I
The software interface contains a 5 word deep Write-FIFO
for the control-data registers as well as a 3 word deep Read-
FIFO for the received data. Thus most of the I
can be transmitted to the hardware without the software hav-
ing to wait for empty space in the FIFO.
All address and data fields appearing on the bus are con-
stantly monitored and written into the Read-FIFO. The soft-
ware can then check these data in comparison with the
scheduled data.
Every reception of a start or restart condition immediately
empties the Read-FIFO. The Read-FIFO stops if it is full. It’s
not overwritten, further received data are lost.
If a read instruction is handled, the interface must send the
data word 0xFF so that the responding slave can insert its
data. In this case the Read-FIFO contains the read-in data.
If telegrams longer than 3 bytes (1 address, 2 data bytes) are
received, the software must check the filling condition of the
Write-FIFO and, if necessary, fill it up and read out the
Read-FIFO. A variety of status flags is available for this pur-
pose:
– The ‘half full’ flag I2CRSx.WFH is set if the Write-FIFO is
– The ‘empty’ flag I2CRSx.RFE is set if there is no more
164
2
Module
Name
I2C0
I2C1
C-bus cycle is generated: start, data, stop, with or without
filled with exactly three bytes.
HW Options
Item
U2.0 CAN0/SCL0 output multiplexer PM.U20
U2.1 CAN0/SDA0 output multiplexer
Module specific settings
2
C-Bus Master Interface.
2
C is in standby mode, i.e. the block
2
2
C telegrams
C slaves).
Address Item
June 12, 2003; 6251-579-1PD
Initialization
SCL0
SDA0
SCL1
SDA1
value. By default, the input deglitcher is on, limiting the
obtainable bit rate to 208.3kbit/s (see Table 26–2).
In standby mode the clock is halted. Programming of the I
registers is possible and the Write-FIFO can be filled.
Prior to operation, proper SW configuration of the U-Ports
assigned to function as I
made. See table 26–1 and section "Ports" for details.
The bit rate and the desired input deglitcher configuration
has to be set up in register I2CMx in order to get into an
active and useful mode. All other registers serve I
purposes.
– The ‘busy’ flag I2CRSx.BUSY is activated by writing any
Moreover the ACK-bit is recorded separately on the bus lines
for the address and the data fields. However, the interface
itself can set the address ACK=0. In any case the two ACK
flags show the actual bus condition. These flags will be reset
with the next I
There is one data acknowledge (DACK) flag available. It indi-
cates the level of the last received ACK bit. It will be cleared
to zero with the reception of a zero and it will be set to one
with the reception of a one within the acknowledge field of a
data byte. Thus, after the stop condition, it indicates whether
the last of the data bytes was acknowledged or not.
The bus activity starts immediately after the first write to the
Write-FIFO. The transmission can be synchronized by an
artificial extension of the low phase of the clock line. Trans-
mission is not continued until the state of the clock line is
high once again. Thus an I
transmission rate to its own abilities.
The figures 26–2, 26–3 and 26–4 show the basic principle
of I
the official I
26.1.4.1. Interrupt Generation and Operation
The transmission of telegrams generates two classes of
interrupts.
– End-of-Telegram interrupt
– Write-FIFO-Half-Full interrupt
data available in the Read-FIFO.
byte to any one of the Write registers. It stays active until
the I
generation.
2
Setting
U2.0 special out, double pull-down mode SR0.I2C0
U2.1 special out, double pull-down mode
U5.1 special out, double pull-down mode SR0.I2C1
U5.2 special out, double pull-down mode
C telegram transmission as a quick reference. Refer to
2
C-bus activities are stopped after the stop condition
2
C documentation for more details.
2
C start condition.
2
C Double Pull-down port has to be
PRELIMINARY DATA SHEET
2
C slave device can adjust the
Enable Bit
2
C data I/O
Micronas
2
C