CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 142

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
Fig. 22–2:
The DMA channel logic contains an input multiplexer which
selects one of four possible DMA request sources (see
Table 22–2 on page 142). The output of this multiplexer sets
a pending flag which is automatically reset when the DMA
cycle is finished. An enable flag (EN) masks the pending flag
output to the priority encoder. A bypass flag (BYP) allows to
redirect DREQ to DINT and thus generate no DMA request
but an interrupt.
The priority encoder assigns each DMA channel a fixed
unique priority (Table 22–1). This is necessary when more
than one DMA channel signals a DMA request at the same
time. The priority encoder outputs the source number with
the highest priority.
The control logic controls the above described three steps of
bus accesses and generates the DMA acknowledge signal
140
DREQx
fDMA
HW Opt.
PINT0
PINT1
DACKx
ENx
Memory
Controller
Once per DMA channel
DMA Controller
DMATx
fSYS
DWAIT
LOCK
DACC
DACK
TRIGx
Mux
&
&
June 12, 2003; 6251-579-1PD
pending
enable
R
D Q
R
S Q
&
(DACKx) which indicates to the requesting module that the
DMA transfer has finished.
Table 22–1:
There are two fundamentally different modes to operate
DMA sequences.
– Self timed describes the situation where the correspond-
– External triggered describes the situation where a third
Priority
(= Channel#)
0
1
2
3
ing I/O module requests a DMA transfer when it’s ready. In
this case the I/O module starts the DMA module when
there is something to transfer and the DMA controller
starts the I/O module after the transfer is finished. This is
the fastest possible way to transfer information via DMA.
Trying to get it faster enforces the danger that one of the
communication partners is not ready.
party requests a DMA transfer. This can be a DMA timer
or a port interrupt. The SW design has to guarantee that
DMA Vec. Base
BYPx
Channel
Control
Logic
DMA
Logic
DMA
DMA Channels
I/O-Module
Default
U-Port
SPI 0
SPI 1
PRELIMINARY DATA SHEET
1
2
3
n
31
Priority
Encoder
src#
Register Name
GD
SPI0D
SPI1D
DINTx
to ICU
A<23:0>
D<31:0>
MAS<0>
MAS<1>
nRW
D<31:0>
Micronas