CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 128

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
19.1.4. Operation of CCC
For entering active mode of the entire CAPCOM module set
the enable bit (Table 19–1 and 19–2).
The CCC will immediately start up-counting with the selected
clock frequency and will deliver this 16bit value to the SUs.
The state of the counter is readable by reading the 16bit reg-
ister CCC, low byte first. Upon reading the low byte, the high
byte is saved to a temporary latch, which is then accessed
during the subsequent high byte read. Thus, for time stamp
applications, read consistency between low and high byte is
guaranteed.
The CCC is free running and will overflow from time to time.
This will cause generation of an overflow interrupt event. The
interrupt (CCCxOFL) is directly fed to the Interrupt Controller
and also to all SUs where further processing takes place.
19.1.5. Operation of Subunit
19.1.5.1. Compare and Output Action
To activate a SUs compare logic the respective 16bit com-
pare register CCx has to be programmed, low byte first. The
compare action will be locked until the high byte write is com-
pleted. As soon as CCx setting and CCC value match, the
following actions are triggered:
– The flag CMP in the CCxI register is set.
– The CCxCOMP interrupt source is triggered.
– The CCxOR interrupt source is triggered if activated.
– The Output Action logic is triggered.
19.1.5.2. Capture and Input Action
The Input Action logic operates independently of the Output
Action logic and is triggered by an external input in a way
defined by field CCxM.IAM. Following Table 19–4 it can com-
pletely ignore events, trigger on rising or falling edge or on
both edges. When triggered, the following actions take place:
– Flag CCxI.CAP is set.
– The CCxOR interrupt source is triggered if activated.
– The 16bit capture register CCx stores the current CCC
Some applications suffer from fast input bursts and a lot of
capture events and interrupts in consequence. If the SW
cannot handle such a rate of interrupts, this could evoke
stack overflow and system crash. To prevent such fatal situa-
tions the Lock After Capture (LAC) mode is implemented. If
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Four different reactions are selectable for the Output
Action signal: according to field CCxM.OAM (Table 19–3)
the equal state will lead to a high or low level, toggling or
inactivity on this output.
Another way to control the Output Action is bit
CCxM.FOL. E.g. rise-mode and force will set the output
pin to high level, fall-mode and force to low level. This forc-
ing is static, i.e. it will be permanently active and may
override compare events. Thus it is recommended to set
and reset shortly after that, i.e. to pulse the bit with SW.
Toggle mode of the Output Action logic and forcing leads
to a burst with clock-frequency and is not recommended.
value, i.e. the “time” of the external event. Read CCx low
byte first. Further capture and input action will be locked
until the subsequent high byte read is completed. Thus a
coherent result is ensured, no matter how much time has
elapsed between the two reads.
June 12, 2003; 6251-579-1PD
bit CCxI.LAC is set, only one capture event will pass. After
this event has triggered a capture, the Input Action logic will
lock until it is unlocked again by writing an arbitrary value to
register CCxM. Make sure that this write only restores the
desired setting of this register.
Programming the Input Action logic while an input transition
occurs may result in an unexpected triggering. This may
overwrite the capture register, lock the Input Action logic if in
LAC mode and generate an interrupt. Make sure that SW is
prepared to handle such a situation.
For testing purposes, a permanent reset (0xFFFF) may be
forced on capture register CCx by setting bit CCxI.RCR.
Make sure that the reset is only temporary.
19.1.5.3. Interrupts
Each SU supplies two internal interrupt events:
1. Input Capture event and
2. Comparator equal state.
In addition to the above mentioned two, the CCC Overflow
interrupt event sets flag CCxI.OFL in each SU. Thus, three
interrupt events are available in each SU. As previously
explained, interrupt events will set the corresponding flags in
register CCxI. Those three interrupt events are masked with
their mask bits in register CCxM and passed to a logical or.
The result (CCxOR) is fed to the interrupt controller as a first
interrupt source. In addition, the Comparator equal (CCx-
COMP) interrupt is directly passed to the interrupt controller
as second interrupt source. Thus a SU offers four types of
interrupts: CCC overflow (maskable ored), input capture
event (maskable ored) and comparator equal state
(maskable ored and non-maskable direct).
All interrupt sources act independently, parallel interrupts are
possible. The interrupt flags enable SW to determine the
interrupt source and to take the appropriate action. Before
returning from the interrupt routine the corresponding inter-
rupt flag should thus be cleared by writing a 1 to the corre-
sponding bit location in register CCxI.
The interrupts generated by internal logic (CCC Overflow
and Comparator equal) will trigger in a predetermined and
known way. But as explained in 19.1.5.2.
signals may cause some difficulties concerning the Input
Capture input as well as interrupt handling. To overcome
possible problems the Input Capture Interrupt flag CCxI.CAP
is double buffered. If a second or even more input capture
interrupt events occur before the interrupt flag is cleared (i.e.
SW was not able to keep track), the flag goes to a third state.
Two consecutive writes to this bit in register CCxI are then
necessary to clear the flag. This enables SW to detect such
a multiple interrupt situation and eventually to discard the
capture register value, which always relates to the latest
input capture event and interrupt.
The internal CAPCOM module control logic always runs on
the clock divider chain f
mode. Avoid write accesses to the CCxI register in CPU
Slow mode since the logic would interpret one CPU access
as many consecutive accesses. This may yield to unex-
pected results concerning the functionality of the interrupt
flags. The following procedure should be followed to handle
the capture interrupt flag CAP:
1. SW responds to a CAPCOM interrupt, switching to CPU
Fast or PLL mode if necessary and determining that the
source is a capture interrupt (CAP flag =1).
2. The interrupt service routine is processed.
0
frequency, regardless of CPU clock
PRELIMINARY DATA SHEET
erroneous input
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