CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 184

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
27.4. Bit Timing Logic
In the bit timing logic the transmission speed (baud rate) and
the sample point within one bit will be configured. By shifting
the sample point it is possible to take account of the signal
propagation delay in different buses. Furthermore, the nature
of the sampling and the bit synchronization can also be
defined.
27.4.1. Baud Rate Pre-scaler
The baud rate pre-scaler is a 6-bit counter. It divides the sys-
tem clock down by the factor 1...64. The output is the clock
for the bit timing logic. This clock TQ
quantum (t
which a bit is subdivided.
27.4.2. Bit Timing
A bit duration consists of a programmable number of TQ
cycles. The cycles are split up into the segments SYNCSEG,
TSEG1 and TSEG2.
27.4.2.1. Bit Timing Definition
Sync.Seg.
It is expected that a bit will begin in the synchronization seg-
ment. If the bit level changes, the resynchronization ensures
that the edge lies inside this segment. The sync.seg is
always one time quantum long.
Prop.Seg.
This part of a bit is necessary to compensate for delay times
of the network. It is twice the sum of the signal propagation
delay on the bus plus input comparator delay plus output
driver delay.
Fig. 27–10:
The baud rate is then calculated as follows:
182
Sync Seg
t
SYNCSEG
BR
BR
t
Bit
=
=
=
Q
------- -
t
---------------------------------------------------------------------------------------- -
( BPR + 1 ) ( 3 + TSEG1 + TSEG2 )
( BPR + 1 ) ( 3 + TSEG1 + TSEG2 )
---------------------------------------------------------------------------------------- -
Bit
1
). The time quantum is the smallest time unit into
Bit Timing Definition
f
f
0
0
1 Timequant
Prop Seg
CLK
t
TSEG1
defines the time
June 12, 2003; 6251-579-1PD
Phase Seg1
t
Bit
CLK
Phase Seg.
Phase segments 1 and 2 are necessary to compensate
phase differences. They can be lengthened or shortened by
resynchronization.
Sample Point
The bus level is read at this point and interpreted as a
received bit.
TSEG1
The CAN implementation combines propagation delay seg-
ment and phase segment 1 to form time segment TSEG1.
TSEG2
TSEG2 corresponds to phase segment 2.
SJW
The synchronization jump width gives the maximum number
of time quanta by which a bit may be lengthened or short-
ened by resynchronization.
27.4.2.2. Bit Timing Configuration
Certain boundary conditions need to be observed when pro-
gramming the bit timing registers. The correct location of the
sample point is especially important with maximum bus
length and at high baud rate.
Sample Point
t
t
t
t
t
t
Bit
Q
SYNCSEG
TSEG1
TSEG2
SJW
=
Phase Seg2
=
=
BPR
------------------- -
t
SYNCSEG
=
=
t
SJW t
TSEG2
f
0
=
+
TSEG1
TSEG2
1
1 t
Q
Q
+
t
+
+
TSEG1
1
1
PRELIMINARY DATA SHEET
t
t
Q
Q
+
t
def. CAN-SPEC
impl. CAN
TSEG2
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