CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 154

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
24.1. Principle of Operation
24.1.1. General
A SPI serves as an 8 or 9 bit wide input/output shift register.
Either an internally or an externally generated clock can be
used to shift data in and out.
The input SPIx-D-IN is connected to the LSB of the shift reg-
ister. The output of the shift register is connected to output
signal SPIx-D-OUT. Thus each time a frame is transmitted by
shifting bits out, bits are shifted in simultaneously and vice
versa. Deglitchers in the data and clock input paths are
active only in external clock mode. The input and output can
be inverted by HW Option.
If the deglitcher is active, input changes polarity after three
consecutive samples have shown the same new polarity.
Thus, a delay of three oscillator clock cycles is introduced.
This feature imposes a limit on the maximum transmission
frequency.
The interrupt is generated after the last bit is clocked out.
The interrupt source output of this module is routed to the
Interrupt Controller logic. But this does not necessarily select
it as input to the Interrupt Controller. Check section “Interrupt
Controller” for the actually selectable sources and how to
select them.
For the effect of CPU clock modes on the operation of this
module refer to section “CPU and Clock System” (see
Table 4–1 on page 37).
24.1.2. Hardware settings
Clock frequency settings and the polarity of the data connec-
tions of the SPIs are settable by HW Options (Table 24–1).
Refer to “HW Options” for setting them.
24.1.3. Initialization
After reset, a SPI is in standby mode (inactive).
Prior to entering active mode, proper SW configuration of the
U-Ports assigned to function as data in- or outputs and clock
in- or outputs has to be made (Table 24–1). Refer to “Ports”
for details.
For entering active mode of a SPI, set the respective enable
bit (Table 24–1).
Prior to operation, the desired clock frequency and telegram
length have to be selected.
24.1.3.1. Clock Source
The SPI can be operated as clock master, using an internally
generated clock, or as clock slave, using an externally gener-
ated clock.
The flag INTERN must be set in the SPIxM Mode register to
operate the SPI as clock master. There are several options
for selection of the internal clock. Each input of a 3 to 1 multi-
plexer can be programmed by HW Options to a different fre-
quency. These three input frequencies F0SPI, F1SPI and
F2SPI are used for all SPIs. The output of the 3 to 1 multi-
plexer is programmed by way of clock selection field (CSF) in
register SPIxM. This clock can be used as shift clock directly,
inverted and divided by 1.5 or 2.5. The shift clock is output by
signal SPIx-CLK-OUT. f
speed in this operation mode.
152
0
can be selected as maximum clock
June 12, 2003; 6251-579-1PD
Table 24–1:
If flag INTERN is zero, the SPI operates as clock slave and
an externally generated clock is used. The external clock is
input by signal SPIx-CLK-IN. This clock must not exceed 1.1
MHz.
The polarity and the sampling edge of the clock is defined by
field SCLK in register SPIxM.
24.1.3.2. Telegram Length
Flag LEN9 in register SPIxM defines the length of a trans-
ferred frame. The ninth bit of the shift register is read or writ-
ten at the location of flag BIT8 in register SPIxM.
Module
Name
All SPIs F0SPI
SPI0
SPI1
HW Options
Item
clock
F1SPI
clock
F2SPI
clock
D in
inver-
sion
D out
inver-
sion
Pres-
caler
D in
inver-
sion
D out
inver-
sion
Pres-
caler
Module specific settings
Address Item
SP0C
SP1C
SP2C
SP0C
SP0C
SMC
SP1C
SP1C
SMC
PRELIMINARY DATA SHEET
Initialization
SPI0-D-
IN
input
SPI0-D-
OUT
output
SPI0-
CLK-IN
input
SPI0-
CLK-
OUT
output
SPI1-D-
IN
input
SPI1-D-
OUT
output
SPI1-
CLK-IN
input
SPI1-
CLK-
OUT
output
Setting
U3.5
special
in
U3.6
special
out
U3.4
special
in
U3.4
special
out
U4.0
special
in
U4.1
special
out
U3.7
special
in
U3.7
special
out
Micronas
Enable
Bit
SR0.
SPI0
SR0.
SPI1