CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 20

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
RESETQ must be pulled up by an external pull-up resistor
(e.g. 10k ).
RWQ 4)
This is an interface signal to external memory.
SCL0 to SCL1
These are the serial clock lines of the I2C modules.
SDA0 to SDA1
These are the serial data lines of the I2C modules.
SEG0.0 to SEG8.5
These pin functions serve as Segment drivers for a 4:1 multi-
plexed LCD.
SEQ (ARM) 1) 2)
This pin outputs the “Sequential address” signal of the ARM.
High indicates that the address of the next memory cycle will
be related to that of the last memory access.
SMA to SMG
These lines are intended for driving stepper motors. They
are the outputs of the SM. Two of these lines together with
an external coil form an H-bridge. Thus each of the signals
SMA to SMG can drive a two phase bipolar stepper motor.
SMA-COMP0, 1, 2, 3 to SMG-COMP0, 1, 2, 3
These lines are comparator inputs that connect to one line
each of the SMA to SMG lines. They serve to distinguish
rotation from stand-still during zero detection in each stepper
motor.
SPI0-CLK-IN, SPI1-CLK-IN
The Serial Synchronous Peripheral Interface Clock input
receives the bit clock from an external master, to shift data in
or out of SPI0 resp. SPI1 in slave mode. This means that the
external master controls the bit stream.
SPI0-CLK-OUT, SPI1-CLK-OUT
The Serial Synchronous Peripheral Interface Clock output
supplies the bit clock of SPI0 resp. SPI1 to an external slave,
to shift data in or out of SPI0 resp. SPI1 in master mode.
This means that the internal SPI controls the bit stream.
SPI0-D-IN, SPI1-D-IN
These are the data input lines of the SPI0 and SPI1 mod-
ules.
SPI0-D-OUT, SPI1-D-OUT
These are the data output lines of the SPI0 and SPI1 mod-
ules.
T0-OUT
The Timer 0 output is connected to the zero output of T0 by a
divide by 2 scaler. The scaler generates a 50% pulse duty
factor.
T1-OUT to T4-OUT
These signals are connected to the overflow outputs of T1 to
T4.
TBIT (ARM) 1)
This pin outputs the TBIT signal of the ARM. High indicates
that the processor is executing the THUMB instruction set.
TCK (ARM)
This pin is the ARM “Test clock” input of the application JTAG
interface.
TDI (ARM)
This pin is the ARM “Test data input” of the application JTAG
interface.
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June 12, 2003; 6251-579-1PD
TDO (ARM)
This pin is the ARM “Test data output” of the application
JTAG interface.
TEST, TEST2
Pins TEST and TEST2 define the source for the Control
Word fetch during reset. Please refer to section “Core Logic”
for detailed information.
TEST2 serves to enable the JTAG interface. Refer to section
“JTAG Interface“ for detailed information.
For normal operation with internal code connect TEST and
TEST2 to System Ground or leave it floating (internal pull-
down).
TMS (ARM)
This pin is the ARM “Test mode select” input of the applica-
tion JTAG interface.
TO2 and TO3
Test outputs.
TRACECLK (ETM) 2)
This is the output of the modified CLK signal of the ETM.
TRACEPKT0 to TRACEPKT15 (ETM) 2)
This is the trace packet port of the ETM.
TRACEPKT15 is pulled low to prevent floating, when full
trace mode is enabled.
TRACESYNC (ETM) 2)
This is the synchronization signal from the ETM, indicating
the start of a branch sequence on the trace packet port.
U0.0 to U8.5
Universal ports are intended for use as digital I/O or as LCD
driver outputs.
UART0-RX, UART1-RX
These are the Receive input lines of UART0 and UART1.
Polarity of the signals is settable by HW options UA0 resp.
UA1.
UART0-TX, UART1-TX
These are the data output lines of UART0 and UART1.
Polarity of signals is settable by HW options UA0 resp. UA1.
UVDD, UVDD1
The pins UVDD and UVDD1 are the positive 5V supply for
the U-Port output stages, for the VDD regulator and the
FVDD regulator. (see Fig. 2–3 for external connection). It
must be buffered by an external capacitor to UVSS resp.
UVSS1.
UVSS, UVSS1
The pins UVSS and UVSS1 are the negative power supply
for the U-Port output stages, and the ground reference for
the VDD and FVDD regulators. They have to be connected
to system ground (see Fig. 2–3).
VDD
This is the output of the internal 2.5V regulator for the inter-
nal digital modules (see Fig. 2–3 for external connection). It
must be buffered by an external capacitor to VSS.
VREF, VREF0, VREF1
These pins are selectable as positive reference inputs for the
ADC. The voltage on these pins should be set to a level
between 2.56 Volts and AVDD.
VREFINT
This pin is the positive reference output of the ADC. The volt-
age at this pin is generated internally (approx. 2.5V) and
PRELIMINARY DATA SHEET
Micronas