CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 197

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
The Transmit Length Register is associated with the whole
field (address or data) which will be written into the transmit
FIFO. It has to be written before the first entry of the field.
BUSY
r1:
r0:
This flag is true as long as there is an entry in the TxFIFO or
transmission is not completed. It is set with the first entry into
the TxFIFO and reset after the transmission of the first T sign
after a telegram.
FLUSH
w1:
w0:
This flag will be reset by the HW autonomously. After FLUSH
29.4. Principle of Operation
29.4.1. Reset
The module reset signal resets all registers and internal HW.
The same does a standby bit in a standby register.
Setting flag RUN in register DGC0 resets all internal HW and
registers with exception of registers DGC0, DGC1, DGS0
and DGS1TA. These registers are accessible all the time,
they are not reset by any setting of the DIGITbus Master
flags.
Internal HW are reset to an inactive state (not transmitting,
not receiving). Internal counters are reset to zero. FIFOs and
shift registers are empty. Internal representations of the bus
line are reset to passive bus level (high).
Fig. 29–6:
Micronas
reset
w
DGTL
r
BUSY
x
x
0
7
FLUSH
EMPTY
SR0.DGB
Reset Structure
0
1
6
Transmitter is Busy
Busy.
Idle.
Flush Tx FIFO
Empty Tx FIFO and abort transmission.
No action.
R
Q
Transmit Length Register
x
x
x
x
5
DGC0.RUN
x
x
4
x
x
R
Q
x
x
x
x
3
0
x
2
x
reset
reset
LEN2 to 0
0
x
x
1
remaining
Registers
registers
Internal
DGC0
DGC1
HW
and
June 12, 2003; 6251-579-1PD
0
x
0
x
Res
Res
wait until EMPTY or TGV becomes true before rewriting
TxFIFO. Setting of FLUSH clears TGV at the same time.
EMPTY
r1:
r0:
LEN
w:
These three bits correspond to the first byte of a bit field.
They define how many bits of this byte carry valid information
and should be transmitted (see Table 29–4 on page 194).
DGTL must be written before the first byte of the actual bit
field is written to the FIFO. It has only to be written once for
each bit field. The overall length of the bit field is not limited.
The first byte of a data field must be written to DGTD.
The first byte of a bit field (with the MSB) which is entered
into DGS1TA or DGTD, may be partially filled. In the following
bytes all bits must contain valid data.
29.4.2. Hardware Settings
The DIGITbus clock and the source of the DIGIT-IN input sig-
nal are settable by HW Options (See table 29–6). Refer to
“HW Options” for setting them.
29.4.3. Initialization
Prior to operation, proper SW configuration of the U-Ports
assigned to module DIGITbus as input and as Double Pull-
down output has to be made. Be aware that it is possible to
have DIGITbus input and output on the same port pin for
easy design of a serial wired-or bus (Single pin bus, Figure
29–1), or to have input and output on separate port pins
which allows a design of an input protection circuit (Double
pin bus, Figure 29–2). See table 29–6 and section "Ports" for
details.
After reset and after setting flag DGB in standby register
SR0, the DIGITbus master is inactive. The global enable flag
RUN must be set together with the appropriate prescaler
entry PSC, to activate the module.
For the effect of CPU clock modes on the operation of this
module refer to section “CPU and Clock System” (see
Table 4–1 on page 37).
29.4.3.1. Clock Master
The flag GBC (generate bus clock) must be set, if the DIGIT-
bus master should generate the bus clock. The module acts
now as clock master of the connected DIGITbus system. It
outputs a stream of T-signs.
w
DGTD
x
7
x
6
Tx FIFO is Empty
No transmit telegram in FIFO.
Transmit telegram in FIFO.
Length of Field
Length of address or data field.
Transmit Data Register
x
5
Transmit Data
x
4
CDC 32xxG-C
x
3
x
2
1
x
x
0
195
Res