CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 18

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
These signals are the compare outputs of the CAPCOM0 to
CAPCOM5 modules.
CE0Q 4)
Chip Enable output signal connects to external program
memory’s CEQ pin. With CR.EFLA set it serves to reduce
program memory’s power consumption when CPU operates
in slow mode. Active LOW.
CE1Q 4)
Chip Enable output signal connects to external RAM or Boot
ROM memory’s CEQ pin and reduces it’s power consump-
tion when CPU operates in slow mode. Active LOW.
CO0, CO0Q, CO1
These signals provide frequency outputs. They are con-
nected to internal prescaler and multiplexer. They can be
hard wired by HW Option. Refer to section “Hardware
Options” for setting the CO0/CO1 options and section “CPU
and Clock System” setting the Clock Out 0 Selection register.
For testing purposes it is possible to drive clocks and other
signals of internal peripheral modules out of CO0 and CO1.
Selection is done via register TST2.
D0 to D31 (ARM) 4)
These 32 signals are the original CPU bidirectional Data Bus
lines. They provide the 32bit data bus for use during data
exchanges between the microprocessor and external mem-
ory or peripherals.
DBGACK (ARM)
This is the debug acknowledge output signal of the ARM.
When high indicates ARM is in debug state.
DBGRQ (ARM) 3)
This is the debug request input of the ARM. It is a level-sen-
sitive input, which when high causes ARM to enter debug
state after executing the current instruction.
DIGIT-IN
This is the receive input line of the DIGITbus module.
DIGIT-OUT
This is the transmit output line of the DIGITbus module.
EMUTRI
This input signal allows to tristate (= high) the interface pins
to external memory (A8 to A23, AMCS1, AICU2 to AICU7,
AMCM21 to AMCM23, CE1Q, FBUSQ and WEQ/RWQ).
ETCK (ARM)
This pin is the ARM “Test clock” input (TCK) of the Emulation
JTAG interface.
ETDI (ARM)
This pin is the ARM “Test data input” (TDI) of the Emulation
JTAG interface.
ETDO (ARM)
This pin is the ARM “Test data output” (TDO) of the Emula-
tion JTAG interface.
ETMS (ARM)
This pin is the ARM “Test mode select” (TMS) input of the
Emulation JTAG interface.
EVDD0 to EVDD8
These 9 lines form the positive power supply of the Emulator
and Trace Bus drivers. EVDD0 to EVDD8 may be connected
to any voltage between 3 to 5.5V. Normally they are con-
nected to FVDD.
EVSS0 to EVSS8
These 9 lines form the negative supply of the Emulator Bus
16
June 12, 2003; 6251-579-1PD
and Trace drivers. EVSS0 to EVSS8 have to be hard wired
to system ground.
EXTERN0, EXTERN1 (ARM) 3)
These are inputs to the ICEBreaker logic of the ARM which
allows breakpoints and/or watch points to be dependent on
an external condition.
EXTTRIG (ETM) 2)
This is a trigger input to the ETM.
FBUSQ 4)
This signal is the reference for access to external synchro-
nous memory. It is active for memory access only.
FSYS
This signal provides the system frequency clock f
the PLL output frequency if PLL is enabled.
FVDD
This is the output of the internal 3.3V regulator for the exter-
nal Flash chip. It must be buffered by an external capacitor to
FVSS.
FVSS
This is the ground reference of the internal 3.3V regulator for
the external Flash chip.
GD0 to GD7
These eight Graphics IC Data lines provide an 8-bit DMA
controlled data link to an external IC.
GOEQ
This Graphics IC Read line provides the control signal for
read accesses via the GD7 to GD0 bus. Active LOW.
GWEQ
This Graphics IC Write line provides the control signal for
write accesses via the GD7 to GD0 bus. Active LOW.
H0.0 to H7.3
The High Current Ports are intended for use as digital I/O
which can drive higher currents than the Universal Ports.
HVDD0 to HVDD3
The pins HVDD0 to HVDD3 are the positive power supply of
the high current ports H0.0 to H7.3. HVDD0 to HVDD3
should be kept at UVDD 0.5V. Be careful to design the PCB
traces for carrying the considerable operating current on
these pins.
HVSS0 to HVSS3
The pins HVSS1 to HVSS3 are the negative power supply
for the high current ports H0.0 to H7.3. HVSS0 to HVSS3
have to be hard wired to system ground. Be careful to layout
sufficient PCB traces for carrying the considerable operating
current on these pins.
INTRES
Test output of internal reset signal. Only for testing and avail-
able only in test mode.
ITSTIN
Test input signal for Interrupt Controller. Only for testing and
available only in test mode.
ITSTOUT
Test output signal of internal peripheral modules. Only for
testing and available only in test mode.
LCD-CLK-IN
The Clock input of the LCD module receives the clock of an
optional external LCD master driver which is used to extend
the LCD driver capability. This input is active if the internal
PRELIMINARY DATA SHEET
Micronas
SYS
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