CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 98

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
GE
r/w1:
r/w0:
Disabling happens as soon as nFIQ is inactive. An active
nFIQ will not be interrupted by clearing GE.
12.3. Principle of Operation
12.3.1. Reset
Clearing standby register flag SR1.FIQ resets the FIQ Inter-
rupt Logic (see Fig. 12–2 on page 95). The registers are
reset to their mentioned values (see Section 12.2. on
page 95) and cannot be modified. The nFIQ output is inac-
tive.
12.3.2. Initialization
Proper configuration of the interrupt sources in the peripheral
modules has to be made prior to initialization of the FIQ
Interrupt Logic.
Initialization is possible after the standby register flag
SR1.FIQ has been set. Now the registers can be modified by
SW. But no interrupt request is generated to the CPU.
The FIQ Interrupt Logic is operable in all CPU speed modes.
12.3.3. Operation
Setting flag CRF.GE enables the FIQ Interrupt Logic. When
an interrupt occurs, execution starts from address 0x1C.
12.3.4. Inactivation
The FIQ Interrupt Logic can be disabled by clearing the glo-
bal enable flag CRF.GE. An active nFIQ will be served, how-
ever, and only future FIQs will be suppressed by clearing the
GE flag.
Clearing the standby register flag SR1.FIQ immediately
resets registers and logic and forces the nFIQ output to inac-
tive.
96
Global Enable FIQ
Enable FIQ.
Disable FIQ.
June 12, 2003; 6251-579-1PD
SEL
r/w:
Table 12–1:
SEL
3
0
1
1
1
1
1
1
1
1
2
x
0
0
0
0
1
1
1
1
1
x
0
0
1
1
0
0
1
1
Select FIQ Source
(Table 12–1)
FIQ Source Selection
0
x
0
1
0
1
0
1
0
1
Switched to nFIQ
Select
None
FIQ0
FIQ1
FIQ2
FIQ3
FIQ4
FIQ5
FIQ6
FIQ7
PRELIMINARY DATA SHEET
ISN
12
13
15
17
19
11
6
5
Interrupt Source
SPI0
WAIT COMP
UART0
PINT2
CC2OR
Timer 2
I2C0
CAN0
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