CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 115

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
16. Timers (TIMER)
Five general purpose timers are implemented. T0 is a 16 bit
timer, T1 to T4 are 8 bit timers.
16.1. Timer T0
Timer T0 is a 16bit auto reload down counter. It serves to
deliver a timing reference signal to the ICU, to output a fre-
quency signal or to produce time stamps.
Fig. 16–1: Timer T0 Block Diagram
16.1.1. Principle of Operation
16.1.1.1. General
The timer’s 16bit down-counter is clocked by the input clock
and counts down to zero. One clock count after reaching
zero, it generates an output pulse, reloads with the content of
the TIM0 reload register and restarts its travel.
For the effect of CPU clock modes on the operation of this
module refer to section “CPU and Clock System” (see
Table 4–1 on page 37).
16.1.1.2. Operation
The clock input frequency is settable by HW option (see
Table 16–1 on page 114).
Prior to entering active mode, proper SW initialization of the
U-Ports assigned to function as T0-OUT outputs has to be
made (Table 16–1). The ports have to be configured Special
Out. Refer to “Ports” for details.
T0 is always active (no standby mode). After reset the timer
starts counting with reload value 0xFFFF generating a maxi-
mum period output signal.
A new time value is loaded by writing to the 16bit register
TIM0, high byte first. Upon writing the low byte, the reload
register is set to the new 16bit value, the counter is reset,
and immediately starts down-counting with the new value.
After reaching zero, on wrapping to 0xFFFF, the counter gen-
erates a reload signal, which can be used to trigger an inter-
rupt. The same signal is connected to a divide by two scaler
to generate the output signal T0-OUT with a pulse duty factor
of 50%.
Micronas
HW Option
T0C
clk
w
r
clk
16 bit Auto-reload
Down counter
Reload-Reg.
16
June 12, 2003; 6251-579-1PD
TIM0
TIM0
underflow
t
clk
Features
– 16bit auto reload counter
– Time value readable
– Interrupt source output
– Frequency output
The interrupt source output of this module is routed to the
Interrupt Controller logic. But this does not necessarily select
it as input to the Interrupt Controller. Check section “Interrupt
Controller” for the actually selectable sources and how to
select them.
The state of the down-counter is readable by reading the
16bit register TIM0, low byte first. Upon reading the low byte,
the high byte is saved to a temporary latch, which is then
accessed during the subsequent high byte read. Thus, for
time stamp applications, read consistency between low and
high byte is guaranteed.
16.1.1.3. Precautions
Use 8bit load/store operations to access Timer 0 register
rather than 16bit access.
A load with a new value within a time period of < t
a scheduled Interrupt Source output signal, can no longer
cancel this signal. It will appear at the Interrupt Source out-
put anyway (See fig. 16–2 for details).
Thus, after loading a new time value, wait at least t
before resetting the Pending Flag P and enabling the inter-
rupt channel.
&
1/2 t
clk
CDC 32xxG-C
res
1/2
T0
Interrupt
Source
T0-OUT
clk
/2 before
113
clk
/2