CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 40

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
Table 4–1:
However, a mean to leave these modes has to be provided.
As the CPU is no longer active, either an external or internal
Wake signal has to be generated. The external Wake costs
no device current, but to generate an internal Wake requires
an internal oscillator and a Real Time Clock (RTC) to run,
which will cost a small amount of supply current
Table 4–2:
4.2.2.1. WAKE Mode
WAKE mode is the most current-saving operation mode. All
device circuits are stopped or powered down except the Port
Wake Module (Table 4–2).
The Port Wake Module allows the CPU to configure up to ten
fixed device ports (see the device pinout for details) as Wake
Ports (WP).
To prepare for WAKE mode, the CPU has to switch off the
RTC and to configure the desired Wake Port(s) (see chapter
“Power Saving Module”, sections “Port Wake Module” and
“RTC Module”).
To enter WAKE mode, the CPU selects WAKE/STBY in reg-
ister SR1.CPUM.
The device will immediately enter WAKE mode by resetting
all circuitry, stopping all clocks, and powering down all regu-
lators and analog circuitry. As long as all Wake Port inputs
are kept at CMOS input levels (V
38
Module
Miscellaneous
JTAG
Embedded Trace Module
1) Possibly affected by f
2) Avoid write access to CCxI
3) Only clocks f5 and slower are available from Clock Divider
4) Don’t access registers or CAN RAM
Operating Mode
Power
Saving
Modes
CPU-Active Modes
WAKE
STANDBY
IDLE
CPU-Active Modes and their effect on peripheral modules
Power Saving Modes and related functionality vs. CPU-Active Modes
Activatable Modules
- Port Wake Module
all WAKE Mode modules plus:
- 4M XTAL or 20..50k RC Oscillator
- Real Time Clock
- Polling Module
all STANDBY Mode modules plus an Auxiliary VDD
Regulator that keeps RAM and Port registers alive.
Other modules according to Table 4–1 are not sup-
ported.
in principle all, for limitations see Table 4–1
0
equaling f
PLL
1
il
=xV
SS
0.3V and
June 12, 2003; 6251-579-1PD
PLL2
Be aware that inadvertently entering a power saving mode,
e.g. by an external electrical overstress (EOS) condition,
when no wake source has been configured previously as
recovery path from this state, renders the device locked in
this power saving mode. Only a RESETQ pin reset or a com-
plete power removal and reapplication recovers the device
from this state. Sufficient external shielding measures must
avoid this hazard.
V
device may be kept in this state indefinitely.
To exit WAKE mode, the previously configured Wake Port
has to switch. Immediately a Wake Reset sequence will be
started internally that pulls the RESETQ pin low and
releases it as soon as all internal reset sources have become
inactive. See chapter “Core Logic” for details on internal
reset sources. After reset, the CPU starts in FAST mode, as
usual.
4.2.2.2. STANDBY Mode
STANDBY mode allows to configure an internal wake source
that wakes after a preselected period. As clock sources,
either a current saving, but imprecise internal RC oscillator,
or the precise, but more current consuming XTAL oscillator
are selectable. Beside the Port Wake Module, these circuits
and the RTC are kept alive (Table 4–2).
ih
=xV
DD
FAST
0.3V), the supply currents will be minimal. The
SRAM,
CAN-RAM
data lost
data lost
data
retained
active
SLOW
PRELIMINARY DATA SHEET
Port Regis-
ters
reset
reset
state
retained
active
DEEP SLOW
Available
Wake
Sources
Wake Ports
Wake Ports
and RTC
Wake Ports
and RTC
Wake
sources
usable as
interrupt
Micronas