CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 81

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
8. JTAG Interface
This module provides JTAG style access to 5 internal scan
chains. These allow testing, debugging, EmbeddedICE and
ETM (Embedded Trace Module) programming. The scan
chains are controlled by a JTAG style Test Access Port (TAP)
controller. For further details on operating TAP controller,
EmbeddedICE and ETM, please refer to ARM7TDMI Data
Sheet (Document Number: ARM DDI 0029), Embedded
Trace Macrocell Specification (Document Number: ARM IHI
0014) and ETM7 Technical Reference Manual (Document
Number: ARM DDI 0158).
8.1. Functional Description
Fig. 8–1: JTAG Interface Block Diagram
The TAP controls the access to the scan chains. Scan chain
0 allows access to the entire periphery of the CPU. Scan
chain 1 is a subset of the scan chain 0. Scan chain 2 allows
programming of the EmbeddedICE debug module. Scan
chain 3 is reserved for the boundary scan of the pads of the
packaged device. Scan chain 6 allows programming of the
ETM.
Table 8–1: Scan Chains
Micronas
DBG.DISA
1) V
2) Availability of Pull-down see section “Packages and Pins“
Number
0
1
2
3
6
JTAG TAP
Controller
ON_5
DD
POR
@ PQFP128
Size [Bit]
105
33
38
-
40
nTRST
1
TMS
TDO
TCK
TDI
&
Function
ARM7 Macrocell
Part of scan chain 0
EmbeddedICE
reserved for Boundary scan
ETM
&
June 12, 2003; 6251-579-1PD
Features
– 2 Interfaces selectable
– Access to CPU periphery
– Access to EmbeddedICE
– Access to Embedded Trace Module
Two interfaces can be selected to access the TAP controller.
The selection has to be done by the control register flag
CR.JTAG and the pins TEST2 and nTRST.
8.1.1. Application JTAG Interface
The application JTAG interface is connected to U-Ports U3.0
to U3.3 and to pin TEST2. The application JTAG interface is
available if enabled and the external circuit layout allows it. It
is enabled if the TEST2 pin is high, the nTRST pin is low and
the flag CR.JTAG is set to one.
In detail, during reset, CR.JTAG is forced to zero and U-Port
U3.3 (JTAG TDO) is tristate. If TEST2 pin is high and
CR.JTAG is set during operation, U-Port U3.3 is forced to
Port, Special, Output mode until programmed by SW. Other-
wise the application JTAG interface couldn’t be operated
without internal SW support. To avoid conflicts between
JTAG mode and SW control on this port bit, never mix these
two modes in one application. The application SW must not
initialize the involved U-Ports if flag CR.JTAG is set to one.
The flag CR.JTAG is modified by the Special Function ROM
too, see section ‘Special Function ROM’ for details.
MUX
1)
0
1
&
2)
CDC 32xxG-C
ETCK
ETMS
ETDI
ETDO
nTRST
TCK/U3.2
TMS/U3.1
TDI/U3.0
TDO/U3.3
TEST2
CR.JTAG
79