CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 150

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
E
r/w1:
r/w0:
BSY
r1:
r0:
Every DACKx signal or access to GD sets this flag and every
DREQx signal clears it again.
SEQ
r1:
r0:
23.3. Principle of Operation
23.3.1. Initialization
Table 23–2 shows the necessary settings of the port configu-
ration registers.
Table 23–2:
Enable the timing generation by setting flag E in register GC.
Enable the clock input and select the desired timing of the
control signals GOEQ and GWEQ in the field GC.TIM. The
minimum high time of the control signals is one fIO cycle.
23.3.2. Data transfer
Data to/from an external device can be transferred directly by
CPU access or, especially for bigger amounts of data and
with help of the external device’s autoincrement address
counter, a DMA sequence can be started. Make sure not to
start a GB transfer unless the flags DTA, SEQ and BSY are
zero.
23.3.2.1. DMA Write Sequence
After initialization of the corresponding DMA channel, set flag
DTA to show others that a DMA sequence was initiated but
not finished and write the first value to be transferred via the
GB to the register GD. The DMA Controller writes the
remaining bytes to register GD and generates an interrupt
when finished. DTA low marks the end of the DMA
sequence.
23.3.2.2. DMA Read Sequence
After initialization of the corresponding DMA channel, set flag
DTA to show others that a DMA sequence was initiated but
148
Register
U5MODE,
U7MODE,
U6MODE
U5NS, U7NS
U6NS
U5TRI,
U7TRI,
U6TRI
Enable
Enable timing generation
Disable timing generation
Busy
GB timing is active
GB timing is not active
DMA Sequence
DMA sequence is active
DMA sequence is not active
Port Configurations
Setting
0x00
0x00
0x06
0x00
Mode
Port mode
Normal
Special
Out
June 12, 2003; 6251-579-1PD
Every DACKx or access to GD signal sets this flag and the
DINTx signal clears it again.
DTA
r1:
r0:
w1:
w0:
This flag indicates the end of a DMA sequence. It has to be
set by SW before a DMA sequence is started. It is cleared by
signal DINTx.
not finished and read the register GD. The DMA Controller
reads the remaining bytes from register GD and generates
an interrupt when finished. DTA low marks the end of the
DMA sequence.
23.3.2.3. CPU Write Access
Writing the byte to register GD is sufficient. The end of the
transfer is indicated by flag BSY.
23.3.2.4. CPU Read Access
The read access must be initiated by a dummy read access
to register GD. After BSY is low the desired byte can be read
from register GD. This last step automatically initiates the
next read timing of the GB logic. If this is not desired,
because GOEQ stays active until the next access to GD,
after BSY became low, first disable the GB timing generation
by clearing flag E in register GC and then read register GD.
23.3.3. Inactivation
Inactivation is easily done by writing GC.TIM to zero. Make
sure not to switch off the GB as long as a transfer is active
(DTA or SEQ or BUSY are set).
23.3.4. Precautions
A write to register GD alters the universal ports data latches
U5D and U7D even if the GB is disabled (GC.TIM = 0).
DMA Transfer Active
DMA sequence started
DMA sequence is finished
Set DTA
No action
PRELIMINARY DATA SHEET
Micronas