CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 123

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
18. Pulse Frequency Modulator (PFM)
The PFM generates a signal with variable frequency and
variable pulse width. Together with external elements it may
serve to generate a negative voltage for LCD elements.
Fig. 18–1:
18.1. Principle of Operation
18.1.1. General
The pulse width and the period counter start synchronously
with down-counting. As long as the pulse width counter is
running, it’s zero output is LOW. When this counter reaches
zero it stops counting and sets the zero output to HIGH.
When the period counter reaches zero, it reloads both
counters, which starts a new count cycle. The zero output of
the pulse width counter can be driven out directly or inverted
via pin PFMx.
The module is operable in PLL, FAST and SLOW mode. As
long as PF0C is available it is also operable in DEEP SLOW
mode. See also chapter “CPU and Clock System” for further
details.
18.1.2. Hardware Settings
The clock input frequency PF0C is settable by HW option
(see Table 18–1).
Micronas
HW Option
SR1.PFMx
PF0C
PFM Block Diagram
1
0
clk
clk
en
ld
ld
16 Bit Down Counter
8 Bit Down Counter
16 Bit Reload-reg.
8 Bit Reload-reg.
June 12, 2003; 6251-579-1PD
Pulse Width
zero
zero
Period Length
Features
– Pulse width and period separately controllable
– Pulse width and period counters operate with HW option
– Output polarity selectable
– Standby mode
Table 18–1:
18.1.3. Initialization
Prior to entering active mode, proper SW initialization of the
U-Ports assigned to function as PFMx output has to be made
(Table 18–1). The ports have to be configured Special Out.
Refer to “Ports” for details.
HW Options
Item
Input
clock
Input
clock
1) Make sure that flag LE in register ANAU is set to zero,
otherwise an internal test signal is output at this pin.
selectable clock
1
Address
PF0C
PF0C
Module specific settings
0
1
Initialization
Item
PFM0
PFM1
1
CDC 32xxG-C
1
0
Setting
U5.0
and/or
U1.7
special
out
U7.5
special
out 1)
PFMx.INV
PFMx
Enable Bit
SR1.PFM0
SR1.PFM1
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