CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 82

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
8.1.2. Emulation JTAG Interface
The emulation JTAG interface is connected to dedicated pins
of the emulation parts (CPGA257 package). Series parts
(PQFP128 package) do not provide this interface. It is
enabled as long as the application JTAG interface is dis-
abled.
8.1.3. Boundary Scan
The boundary scan is not implemented in this IC.
8.1.4. Pin TEST2
Refer to section “Electrical Characteristics” for details.
Besides JTAG, the pin TEST2 controls the behavior of the IC
during reset. Refer to section “Core Logic” for further details.
8.1.5. External HW Requirements
The external circuit has to make sure that the TEST2 pin is
driven to the required level during reset and switched to the
JTAG probe after reset so that the pin can be controlled by
the probe. This can be done by connecting a driver between
8.2. Registers
8.3. External Circuit Layout
The emulation JTAG interface uses TTL level input compara-
tors. The emulation JTAG inputs ETCK, ETMS, ETDI and
nTRST need external pull-up resistors to EVDD. This has to
be done in a way, that the TAP controller sees a logic one if
the emulation JTAG interface is enabled but not driven.
The application JTAG interface shares its input and output
pins with the I/O of U-Ports. The external circuit layout has to
be done carefully in order to guarantee functionality of the
JTAG interface. As long as the application JTAG interface is
enabled and not driven, the TAP controller inputs TMS and
8.4. JTAG ID
The JTAG ID is not implemented in this IC.
The JTAG TAP controller contains a HW coded JTAG ID
which can be read serially via the JTAG interface. The CPU
can’t access this ID.
80
w
DBG
x
7
x
6
Debug Register
x
5
0x01 (after UVDD power-up)
x
4
x
3
x
2
x
1
DISA
June 12, 2003; 6251-579-1PD
0
0
Res
Offs
JTAG probe and TEST2 pin and disabling the driver during
reset. The reset state can be detected by sensing the
RESETQ pin. The threshold voltage of the external logic
must be higher than the minimum recommended Reset Inac-
tive Input Voltage RV
74HC14 schmitt trigger (not the HCT variant!). Figure 8–2
shows an example of the external circuit.
Fig. 8–2: TEST2 Pin External Circuit Diagram for Applica-
tion JTAG Interface
DISA
w1:
w0:
TDI shall see logic one level. If it is enabled and driven, the
external application circuit shall not influence proper opera-
tion of the JTAG interface. The external host must be able to
drive the levels at the inputs TCK, TMS and TDI to CMOS
logic one and logic zero levels and it must be the only source
of these signals. The TAP controller must be able to drive the
output TDO to both CMOS levels, logic one and zero, and
must be the only source of this signal.
Common JTAG tools expect to see pull-up resistors at
nTRST (TEST2), TCK,TMS and TDI.
Bits 1 to 19 are manufacturer defined. Bits 0 and 20 to 31 are
ARM defined.
nTRST
from
host
UVDD
4k7
Disable Voltage Generators, JTAG/ETM
Standard: Debug data lost during power
saving modes because supply is disabled.
Survive mode: Regulators don’t shut off power
during power saving modes, and debug data
survive wake reset.
NC7SZ125
UVDD
74HC14
im
(1.5V) of this IC. Use for example
PRELIMINARY DATA SHEET
4k7
Jumper defines
reset level
Micronas
RESETQ
TEST2