CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 63

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
During power saving modes, internal resets are generated
that are not routed to pin RESETQ. However, a wake-up
from any power saving mode is treated as a fifth internal
reset source and does pull RESETQ low. See the chapter on
the Power Saving Module for details.
All these five internal resets are directed to the open drain
output of pin RESETQ. Thus a “wired or” combination with
external reset sources is possible. The RESETQ pin is cur-
rent limited and therefore large external capacitances may
be connected.
All internal reset sources initially set a reset request flag.
This flag activates the pull-down transistor on the RESETQ
pin. An internal Reset Extension Timer starts, as soon as no
internal reset source is active any more. It counts 2048 f
periods (for alternative settings refer to HW options register
CR) and then resets the reset request flag, thus releasing the
RESETQ pin.
As long as the Reset Comparator on the pin RESETQ
detects the low level, the overall IC is reset except the PSM/
RTC.
The state of bits 6:0 in register CSW1, read directly after a
system reset, allows to distinguish the cause of this last sys-
tem reset (Table 6–5).
6.5.2.1. Supply Supervision
A UV
POR, or an overload condition in the internal VDD or FVDD
Regulators will permanently pull the pin RESETQ low and
thus hold the IC in reset (see Fig. 6–3 on page 62). This
reset source can be enabled/disabled by flag CMA in register
CSW0 (see Section 6.5.2.2. on page 61).
6.5.2.2. Clock Supervision
The Clock Supervision monitors the frequency at the oscilla-
tor input XTAL1 and also the frequency f
at the input of the central clock divider (see Fig. 4–2).
Fig 6–2 shows how the Clock Supervision works:
upon power-up the crystal oscillator starts to build up oscilla-
tion on pins XTAL1 and XTAL2. Initially, the internally avail-
able f
The internal Reset Extension Timer starts counting f
clocks as soon as ~20 uninterrupted clocks, having a certain
minimum amplitude, are detected, but it is reset when a
drop-out period of ~5us appears. When the XTAL oscillation
and thus f
the Reset Extension Counter may finish its travel and finally
release pin RESETQ.
Micronas
DD
XTAL
level below the Supply Supervision threshold VREF-
XTAL
/f
SUP
and f
clock may show fluctuations and drop-outs.
SUP
have been stable over 2048 clocks,
SUP
that is present
June 12, 2003; 6251-579-1PD
XTAL
XTAL
Fig. 6–2:
Frequencies below the clock supervision threshold of
approx. 200kHz will permanently pull the pin RESETQ low
and thus hold the IC in reset (see Fig. 6–3 on page 62). This
reset source can be enabled/disabled by flag CMA in register
CSW0.
Frequencies exceeding the specified IC frequency are not
detected.
Clock and Supply Supervision are active after reset, but can
be enabled/disabled by the clock-monitor-active flag CMA of
register CSW0. Setting CSW0.CMA to 0 is recommended for
test and evaluation purposes only.
The Clock Supervision is switched off during power saving
mode. Every time the Clock Supervision was switched off
(VDD Regulator is off) and is switched on again, it outputs a
reset signal and sets flag CSW1.CLM.
Count
RESETQ
Reset
f
2048
XTAL
Ext.
V
0
0
XTAL1
UVDD
<20
Clock Supervision: Principle of Operation
~20
CDC 32xxG-C
~20
61