CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 48

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
Table 4–7:
Frequencies (MHz)
4.7. PLL/ERM Application Notes
4.7.1. PLL Jitter
The embedded PLL synchronizes every n-th f
the externally applied f
smoothly tries to cancel out influences from power supply
noise and f
this permanent re-synchronization process is expected to
introduce some nanoseconds of phase jitter to f
It is important to note that PLL jitter does not introduce a
noticeable frequency error, because the phase stays locked
to the f
only within the same tight limits. Even with a PLL induced f
jitter of
between two f
– spaced 1us apart is (1us 2 5ns)/1us= 1%,
– spaced 1ms apart is (1ms 2 5ns)/1ms= 10ppm,
– spaced 1s apart is (1s 2 5ns)/1s= 0.01ppm,
and so forth.
4.7.2. ERM “Jitter”
The effect of the ERM on f
to that of PLL jitter in that it adds limited phase modulation.
However, this ERM induced jitter is especially tailored to
improve the electromagnetic emission properties of the
device. Section 4.5.1. gives details on setting the maximum
phase delay:
– 7.5ns (weak) translates to 3.75ns of f
– 12.5ns (normal) translates to 6.25ns of f
– 20ns (strong) translates to 10ns of f
From these figures it is evident, that ERM introduces a jitter
that, in its extent, is comparable to PLL jitter. Both influences
may be added to estimate the combined PLL/ERM effect on
I/O module operation.
4.7.3. Influence of PLL/ERM on Module Operation
DIGITbus, SPI and I2C synchronize external devices to one
master clock. Their operation is hardly impeded by PLL/ERM
jitter.
Modules like UART and CAN communicate with external
fixed-frequency devices, and there is a maximum frequency
46
f
4
5
XTAL
XTAL
5ns, the maximum observable frequency error
CPU
f
12
20
15
XTAL
SYS
reference and fluctuates, even over long times,
PLL2 and ERM Modes: Settings Sacrificing Unlimited Operation of Peripheral Modules and Resulting Operating
IO
clocks
fluctuations. Depending on the application,
PLLC.
PMF
2
4
2
XTAL
IO
phase and frequency is similar
Flash
f
6
12
10
7.5
BUS
signal. This synchronization
WSR
0x11
0x00
0x11
0x11
IO
IO
jitter.
jitter,
IO
jitter,
I/O
f
f
4
5
IO
IO
0
SYS
.
=
June 12, 2003; 6251-579-1PD
cycle to
IOC.
IOP
2
4
2
IO
ERMC.EOM = 1
Weak
0
0
0
0
offset between transmitting and receiving station, that can be
tolerated without transmission error.
Viewed from the receiving station, a frequency offset of the
transmitting station is tolerable, as long as over the length of
a complete telegram, every bit can still be detected unambig-
uously. Once the tolerable frequency offset is exceeded,
communication is fatally disturbed. This tolerable offset is
dependent on the capability of the involved circuitry to detect
and compensate for frequency offset.
In the further discussion, the clock tolerance TOL is defined
as percentage offset of the actual from the nominal fre-
quency
Note that each transmitting and receiving station are allowed
this same tolerance from nominal:
f
The resulting maximum offset between transmitter and
receiver thus is 2 x TOL.
4.7.3.1. UART
Let’s consider the tolerable frequency offset in the case of
the UART.
The Baud Rate frequency is always the sample clock fre-
quency, divided by 8. The max. telegram length is 12 bit. A
transmitter frequency offset is tolerable as long as 12*8
receiver sample clocks equal 12*8 transmitter sample
clocks,
f
PLL and ERM jitter claim a certain portion of this tolerable
offset. Let’s assume that both influences add up to 15ns of
f
With the Baud rate set to 1MBaud, f
With this setting, PLL and ERM jitter consume
2*15ns/375ns=8%
of the tolerable transmitter frequency offset and reduce TOL
to 1.48%.
trans
Trans
IO
10
6
5
7
jitter, and that f
=f
=f
Normal
nom
Rec
0
0
0
0
which
(12*8/(12*8 3))=f
TOL and f
10
15
13
5
Strong
IO
0
0
0
0
gives
=f
TOL
rec
0
15
15
15
=8MHz.
=f
5
nom
=
PRELIMINARY DATA SHEET
a
Rec
ERMC.EOM = 2 or 3
Weak
10
-------------------------- -
6
6
7
f
act
TOL
transmitter
f
3.23% and TOL= 1.61%.
nom
–
f
3
2
5
4
nom
SAMPLE
Normal
10
10
17
13
frequency
5
2
8
7
equals 8MHz.
Strong
16
16
28
21
Micronas
11
8
2
8
of
3