CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 44

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
– different wait state values for sequential and nonsequen-
– allows 8, 16 and 32bit memory accesses from CPU
– supports access to 8, 16 and 32bit wide memory
– allows big or little endianness.
4.4.1. Principle of Operation
4.4.1.1. General
The Memory Controller contains a Memory Mapping Unit
(MMU) to control the mapping of the whole memory system,
a Wait State Register (WSR) to initialize the various wait
states, a Final State Machine and a Wait State Counter to
control the various types of access and wait states.
4.4.1.2. Initialization
After reset, the CPU runs in FAST mode, the Wait State
Counter is disabled due to SR1.CPUM=1 and no wait states
for access to asynchronous memory are programmed. The
access to the synchronous memory (I/O) works right after
reset, independent from any setting by software. Endian
mode is set by the Control Word via bit CR.ENDIAN.
First, initialize the wait state register WSR (cf. Table 4–6).
Then the PLL or PLL2 mode may be enabled, if desired.
Don’t change the wait state register while in PLL mode, this
may lead to a memory access with undetermined wait state
count in the following cycle.
4.4.1.3. Operation
With proper SW initialization, the Memory Controller is also
ready to access the asynchronous memory systems (ROM/
Flash, RAM, Boot ROM).
The MMU decides from the address and the CR setting,
which area in memory space contains a 8, 16 or 32bit mem-
ory system. It preselects the different types of memory
(ROM/Flash, RAM, Boot ROM and I/O-Pages) and com-
putes the address for ROM/Flash minus 200000hex, if ROM/
Flash should be mapped to base address 200000hex.
In presence of a Patch Module, the PATCHACC signal from
the Patch Module signals to the MMU that the next access
will be an access to the Patch Module instead to normal
ROM/Flash.
The DMAACC signal from the DMA Module signals, that the
next address value will be driven by DMA and not by CPU.
Due to the fact that DMA always reads/writes a location in
ROM/Flash, RAM or Boot ROM and writes/reads to a loca-
tion in the I/O area within the same bus cycle, the MMU also
preselects the I/O area and the Memory Controller times the
whole DMA cycle to the restrictions of the slow synchronous
I/O area.
42
tial accesses to asynchronous memory
June 12, 2003; 6251-579-1PD
Fig. 4–5:
4.4.1.4. Inactivation
Returning
(SR1.CPUM=1) will immediately switch the CPU to FAST
mode and change any further access to asynchronous mem-
ory to non-wait-state operation.
SR1.CPUM=3, 7
CR.ENDIAN
PATCHACC
DMAACC
CR.MAP
ICUACC
CR.PSA
CPU Bus
Memory Controller Block Diagram
Addr
the
f
SYS
f
IO
Memory
SWS
WS Counter
PRELIMINARY DATA SHEET
Controller
Memory
Bridge
Bridge
Bridge
Controller
Mux
NWS
to
predecrom
predecram
predecboot
predecio
waitq
I/O
ROM
Boot
Emu
Flash
FAST
WSR
Micronas
mode