CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 176

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
XREF
r/w0:
r/w1:
able.
REF1
r/w0:
r/w1:
nal.
REF0
r/w0:
r/w1:
ITX
r/w0:
r/w1:
Every flag of the CANxESTR can be enabled/disabled gen-
erating an interrupt by modifying the corresponding flag in
register CANxESM.
EGDM
r/w0:
r/w1:
174
r/w
r/w
r/w
CANxICR
CANxOCR
CANxTEC
CANxREC
CANxESM
r
r
EGDM
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x
x
0
x
x
1
7
7
7
7
7
ECTV
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0
0
1
6
x
6
x
6
6
6
Use Reference for RxD1
Use Reference for RxD0
External Reference
The internal reference is used.
The external reference is used where avail-
RxD is used as inverted input signal.
Supply voltage is used as inverted input sig-
RxD is used as input signal.
Ground is used as input signal.
Inverted transmission
Tx output is not inverted.
Enable Good Morning
Disable.
Enable.
output is inverted.
EECT
rsvd
rsvd
Input Control Register
Output Control Register
Transmit Error Counter
Receive Error Counter
Error Status Mask Register
x
x
0
0
1
5
5
5
5
5
Counter Bit 7 to 0
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EBIT
0
0
1
4
x
4
x
4
4
4
Counter Bit 6 to 0
ESTF
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rsvd
x
x
0
0
1
3
3
3
3
3
ECRC
XREF
rsvd
0
0
0
1
2
2
x
2
2
2
EFRM
REF1
rsvd
0
x
0
0
1
1
1
1
1
1
EACK
June 12, 2003; 6251-579-1PD
REF0
ITX
0
0
0
0
1
0
0
0
0
0
Res
Res
Res
Res
Res
ECTV
r/w0:
r/w1:
EECT
r/w0:
r/w1:
EBIT
r/w0:
r/w1:
ESTF
r/w0:
r/w1:
ECRC
r/w0:
r/w1:
EFRM
r/w0:
r/w1:
EACK
r/w0:
r/w1:
The Capture Timer is incremented with a clock pulse derived
from the CAN bus. Because it can only be read byte-wise,
the low byte must be read first. The corresponding high byte
is latched at the same time. When CANxCTIM overflows, the
flag CTOV in the error status register is set. The Capture
Timer will not be incremented during CAN module sleep
mode (SLP = 1).
CANxCTIM
r
r
0
7
0
6
Enable Capture Time Overflow
Disable.
Enable.
Enable Error Counter Level
Disable.
Enable.
Enable Bit Error
Disable.
Enable.
Enable Stuff Error
Disable.
Enable.
Enable CRC Error
Disable.
Enable.
Enable Form Error
Disable.
Enable.
Enable Acknowledge Error
Disable.
Enable.
Capture Timer
0
5
Timer Bit 15 to 8
Timer Bit 7 to 0
0
4
PRELIMINARY DATA SHEET
0
3
0
2
0
1
Micronas
0
0
1
0
Res