CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 38

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
4.2.1. CPU-Active Modes
The CPU can be operated in five different CPU-active modes
(Table 4–1). Core modules that are also affected by CPU-
active modes are:
1. Interrupt Controller with all internal and external interrupts
2. RAM, ROM/Flash and DMA
3. Watchdog
Table 4–1 shows the operability of the peripheral modules in
the various CPU-active modes.
When switching between modes, neither interrupts (see Sec-
tion 11.4.4. on page 92) nor DMA (see Section 22.3. on
page 142) accesses are allowed, to prevent undefined
behavior of the clock system.
4.2.1.1. FAST Mode
After reset the CPU is in FAST mode. The CPU clock and the
I/O clock both equal the oscillator frequency f
Internal clock frequencies higher than f
in this mode. Modules requiring f
not work properly, as f
Returning CPU from any other CPU-active mode to FAST
mode is done by selecting the appropriate mode in the
standby registers field SR1.CPUM (Table 4–3).
4.2.1.2. PLL Modes
To increase CPU performance, a PLL allows to multiply
f
its speed is automatically reduced only for accesses to
slower modules (ROM/Flash, I/O).
Table 4–6 gives recommended settings for control registers
and the various resulting operating frequencies for the PLL
mode. These recommended settings achieve f
f
modules.
A PLL2 mode allows bypassing of the first stage of the
divider chain. It allows a clock system with f
f
operation of peripheral circuits has to be sacrificed (see
Table 4–7 for settings).
In both PLL modes, the EMI Reduction Module (ERM) can
be operated, which reduces electromagnetic energy emis-
sion (see Section 4.5. on page 43).
Activating the PLL modes is done in FAST mode by the fol-
lowing routine:
1. For initialization, choose a pair of settings for the clock
multiplication factor and the clock prescaler from Tables 4–6
or 4–7 and write them to PLLC.PMF and IOC.IOP.
2. When coming from SLOW or DEEP SLOW mode, allow
t
other cases, wait the time of t
3. Wait for at least t
set, to make sure that the PLL has locked.
4. Disable ICU and DMA, if active.
5. Enable PLL mode by writing 0x03, or PLL2 mode by writ-
ing 0x07 to SR1.CPUM (32-bit access only).
6. As the System Frequency Divider and the Prescaler need
some time to synchronize, the PLL mode is not active until
36
XTAL
1
0
REFINT
= f
= f
XTAL
1
. The CPU will operate at this higher frequency f
= f
to elapse for VREFINT and BVDD to set up. In all
XTAL
and so forth, for unlimited operation of peripheral
for special applications, where the unlimited
SUPLL
0
is set to f
before checking PLLC.LCK to be
BVDD_su
1
0
= f
= 2f
XTAL
for BVDD to set up.
XTAL
XTAL
.
SYS
for operation will
are not available
XTAL
= n*f
0
.
June 12, 2003; 6251-579-1PD
= 2*f
XTAL
SYS
XTAL
and
and
,
PLLC.PLLM reads as 1.
7. At this point the ERM may be activated (see Section 4.5.3.
on page 43) and ICU and DMA may be (re-)enabled.
Returning to FAST mode is done by the following routine:
1. Deactivate the ERM, if active (see Section 4.5.4. on
page 43).
2. Disable ICU and DMA, if active.
3. Return to FAST mode by setting SR1.CPUM to 0x01 (32-
bit access only).
4. Wait for PLLC.PLLM to read as 0.
5. Now the ICU and DMA may be (re-)enabled and the pro-
gram may resume.
Attention: The PLL modes must be entered and left only via
FAST mode. The registers PLLC.PMF and IOC.IOP may
only be changed in FAST mode.
To reduce the power consumption in other CPU-active
modes than PLL modes, the registers PLLC.PMF and
IOC.IOP should be programmed to zero.
4.2.1.3. SLOW Mode
To considerably reduce power consumption, the user can
reduce the internal CPU clock frequency to 1/128 of the nor-
mal f
reduced to 1/128 of f
Some modules must not be operated during SLOW mode
(e.g. CAN). Refer to module sections for details (see
Table 4–1 on page 37).
Internal clock frequencies higher than f
in this mode. Modules requiring f
not work properly, as f
For switching between SLOW and FAST modes, use the fol-
lowing routine:
1. Disable ICU and DMA, if active.
2. Select the desired mode in the standby registers field
CPUM (Table 4–3). The new f
3. Now the ICU and DMA may be (re-)enabled and the pro-
gram may resume (no waiting time).
4.2.1.4. DEEP SLOW Mode
To further reduce power consumption beyond SLOW mode,
DEEP SLOW mode also disables most of the internal periph-
eral clocking system. Table 4–1 shows which peripheral
modules can be operated in DEEP SLOW mode.
Only peripheral module clocks f
from the divider chain. T0 can be operated only with this limi-
tation.
For switching between DEEP SLOW and FAST modes, use
the routine given for SLOW mode.
4.2.2. Power Saving Modes
All Power saving modes are activated by the CPU. The com-
plete core logic will immediately terminate operation and
power will be removed. The result is a device current con-
sumption that is greatly reduced, to the amount of leakage
currents.
XTAL
value. In this SLOW mode, program execution is
XTAL
0
is set to f
.
PRELIMINARY DATA SHEET
BUS
0
1
5
is effective immediately.
= 2*f
= f
and slower are available
XTAL
XTAL
XTAL
.
are not available
for operation will
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