CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 43

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
LCK special output by selection in fields ANAU.LE and
ANAU.LS (UVDD Analog Section).
The block multiplies f
PLL Control register PLLC allows to set the desired value.
Fig. 4–3:
4.3.2. I/O Clock Prescaler
This prescaler derives the clock for the peripheral modules
(the I/O clock f
by an integer number m. I/O Clock Control register IOC
allows to set the desired value. m is recommended to be set
equal to n/2.
4.3.3. Divider Chain and Clock Outputs CO0 and
CO1
The peripheral module divider chain receives f
supplies the various modules with their specific clocks. Each
stage of the divider chain divides its input clock by two. Thus
only powers of two of the divider chain input clock are obtain-
able for the peripheral modules.
Table 4–3 shows the effect of CPU-active mode selection on
the divider output frequencies f
modes FAST, PLL and SLOW, with n = 2m (which is recom-
mended), f
divided clocks are unaffected by switching between these
modes.
Section “HW Options” gives details about HW option con-
trolled clocks, their selection and their activation.
Note that specifying 1/1.5 and 1/2.5 prescaled clocks result
in clock signals with 33% resp. 20% duty factor.
Two Clock Output signals CO0 and CO1 provide external
visibility of internal clocks (Figure 4–4). Clocks are selected
by register CO0SEL.
4.4. Memory Controller
The Memory Controller connects the CPU to the complex
memory system. It controls the various types of access and
wait states.
Micronas
VP ~ f(
f
XTAL
XTAL
1
PLL Block Diagram
always equals f
-
f
REF
IO
Phase
Comp.
REF
) from the system clock f
)
1/(PMF+1)
XTAL
V
P
PMF = 1..15
XTAL
by n = PMF+1 to achieve f
VCO
. Thus f1 and all further sub-
0
through f
SYS
PMF = 0
17
. It divides f
. Note that in
SYS
June 12, 2003; 6251-579-1PD
n f
/m and
XTAL
SYS
SYS
.
Fig. 4–4:
Signal CO0 is the output of a pre-scaler and a 4 to 1 multi-
plexer. Prescaler and input for the multiplexer are selectable
by HW options (see Table 4–4). The output selection of the
multiplexer is done by register CO0SEL, bits CO01 and
CO00. The outputs of the pre-scalers are fed not only to the
ports, but may also serve as interrupt source. The U-Ports
assigned to function as clock outputs (see Table 4–4) have to
be configured Special Out.
The interrupt source output of this module is routed to the
Interrupt Controller logic. But this does not necessarily select
it as input to the Interrupt Controller. Check section “Interrupt
Controller” for the actually selectable sources and how to
select them.
CO0 and CO1 are not affected by SLOW mode.
Table 4–4:
Features
– support of one synchronous- and up to three different
HW Option
HW Option
Clock Out
SMX Out is an output of
the power saving module.
CO0
CO0
SMX Out
f
Signal
CO0
CO1
1) HW Options register flag PM.U15 switches between
CO0Q and CO1 at U1.5 special out.
XTAL
asynchronous memory areas
Mux0
Mux1
CO0SEL.CO00,
CO0SEL.CO01
Clock Outputs Diagram
HW Options
Item
CO0
Prescaler
CO0
CO0
CO1
Prescaler
Clock Out
HW Options and Ports
Mux
4:1
Mux0
Mux1
2
HW Option
Address
CO00C
CO01C
CO1C
1/1.5
1/2.5
1/1.5
1/2.5
1/1
1/1
CDC 32xxG-C
Initialization
Item
CO0
output
CO0Q
output
CO1
output
1
Setting
U1.6, U3.3
or U7.7
special out
U1.5 spe-
cial out 1)
U0.4, U1.5
or U7.6
special
out1)
CO0Q
CO0
CO0
Interrupt
Source
CO1
CO1
Interrupt
Source
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