XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 151

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

9.3.2 Clock Startup from POR or LVI Reset
9.3.3 Clocks in Stop Mode and Wait Mode
MC68HC908AZ60A — Rev 2.0
MOTOROLA
OSC1
PLL
CGMVCLK
When the power-on reset module or the low-voltage inhibit module
generates a reset, the clocks to the CPU and peripherals are inactive
and held in an inactive phase until after 4096 CGMXCLK cycles. The
RST pin is driven low by the SIM during this entire period. The bus clocks
start upon completion of the timeout.
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows
CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do
not become active until after the stop delay timeout. This timeout is
selectable as 4096 or 32 CGMXCLK cycles. See
164.
In wait mode, the CPU clocks are inactive. Refer to the wait mode
subsection of each module to see if the module is active or inactive in
wait mode. Some modules can be programmed to be active in wait
mode.
MONITOR MODE
SELECT
CIRCUIT
CLOCK
USER MODE
BCS
CGM
PTC3
Figure 9-3. CGM Clock Signals
System Integration Module (SIM)
÷
2
A
B S*
*When S = 1,
CGMOUT = B
CGMXCLK
CGMOUT
SIM Bus Clock Control and Generation
System Integration Module (SIM)
÷
SIM COUNTER
2
SIM
Stop Mode
GENERATORS
BUS CLOCK
Technical Data
on page
151