XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 22
XC908AS60ACFU
Manufacturer Part Number
XC908AS60ACFU
Description
MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
Manufacturer
Motorola Semiconductor Products
Datasheet
1.XC908AS60ACFU.pdf
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List of Figures
Technical Data
22
18-16 SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . . . . 278
18-17 SCI Data Register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
18-18 SCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . . . . 279
19-1 SPI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 289
19-2 Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . . . . 290
19-3 Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . 293
19-4 Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . 294
19-5 Transmission Start Delay (Master) . . . . . . . . . . . . . . . . . . . . . 296
19-6 Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . . . . 298
19-7 Clearing SPRF When OVRF Interrupt Is Not Enabled . . . . . . 299
19-8 SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . . . 302
19-9 SPRF/SPTE CPU Interrupt Timing . . . . . . . . . . . . . . . . . . . . . 303
19-10 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
19-11 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . . 310
19-12 SPI Status and Control Register (SPSCR) . . . . . . . . . . . . . . .313
19-13 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
20-1 TIMB Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
20-2 TIMB I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 320
20-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 325
20-4 TIMB Status and Control Register (TBSC) . . . . . . . . . . . . . . .331
20-5 TIMB Counter Registers (TBCNTH and TBCNTL) . . . . . . . . . 334
20-6 TIMB Counter Modulo Registers (TBMODH and TBMODL) . 335
20-7 TIMB Channel Status and Control Registers (TBSC0–TBSC1)
20-8 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
20-9 TIMB Channel Registers (TBCH0H/L–TBCH1H/L) . . . . . . . . 341
21-1 PIT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344
21-2 PIT I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
21-3 PIT Status and Control Register (PSC) . . . . . . . . . . . . . . . . . 348
21-4 PIT Counter Registers (PCNTH–PCNTL). . . . . . . . . . . . . . . . 350
21-5 PIT Counter Modulo Registers (PMODH–PMODL) . . . . . . . . 351
22-1 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 354
22-2 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .355
22-3 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . 355
22-4 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
22-5 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .357
22-6 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . 358
22-7 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
List of Figures
MC68HC908AZ60A — Rev 2.0
MOTOROLA
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