XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 306

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

Serial Peripheral Interface (SPI)
19.13 I/O Signals
Technical Data
306
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a two-step read/write clearing procedure. If software
does the first step on such a bit before the break, the bit cannot change
during the break state as long as BCFE is at logic 0. After the break,
doing the second step clears the status bit.
Since the SPTE bit cannot be cleared during a break with the BCFE bit
cleared, a write to the data register in break mode will not initiate a
transmission nor will this data be transferred into the shift register.
Therefore, a write to the SPDR in break mode with the BCFE bit cleared
has no effect.
The SPI module has four I/O pins and shares three of them with a
parallel I/O port.
The SPI has limited inter-integrated circuit (I
software support) as a master in a single-master environment. To
communicate with I
when the SPWOM bit in the SPI control register is set. In I
communication, the MOSI and MISO pins are connected to a
bidirectional pin from the I
to V
•
•
•
•
•
DD
MISO — Data received
MOSI — Data transmitted
SPSCK — Serial clock
SS — Slave select
V
.
SS
Serial Peripheral Interface (SPI)
— Clock ground
2
C peripherals, MOSI becomes an open-drain output
2
C peripheral and through a pullup resistor
2
C) capability (requiring
MC68HC908AZ60A — Rev 2.0
2
C
MOTOROLA