XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 24

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

List of Figures
Technical Data
24
23-20 Receiver Interrupt Enable Register (CRIER) . . . . . . . . . . . . . 420
23-21 Transmitter Flag Register (CTFLG) . . . . . . . . . . . . . . . . . . . . 421
23-22 Transmitter Control Register (CTCR) . . . . . . . . . . . . . . . . . . . 423
23-23 Identifier Acceptance Control Register (CIDAC). . . . . . . . . . . 424
23-24 Receiver Error Counter (CRXERR) . . . . . . . . . . . . . . . . . . . . 425
23-25 Transmit Error Counter (CTXERR). . . . . . . . . . . . . . . . . . . . . 426
23-26 Identifier Acceptance Registers (CIDAR0–CIDAR3) . . . . . . . 427
23-27 Identifier Mask Registers (CIDMR0–CIDMR3) . . . . . . . . . . . . 428
24-1 Keyboard Module Block Diagram
24-2 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
24-3 Keyboard Status and Control Register (KBSCR) . . . . . . . . . . 437
24-4 Keyboard Interrupt Enable Register (KBIER) . . . . . . . . . . . . . 438
25-1 TIMA Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
25-2 TIMA I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 444
25-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 450
25-4 TIMA Status and Control Register (TASC) . . . . . . . . . . . . . . .457
25-5 TIMA Counter Registers (TACNTH and TACNTL) . . . . . . . . . 460
25-6 TIMA Counter Modulo Registers (TAMODH and TAMODL) . 461
25-7 TIMA Channel Status and Control Registers (TASC0–TASC5)
25-8 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
25-9 TIMA Channel Registers (TACH0H/L–TACH5H/L) . . . . . . . . 468
26-1 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
26-2 ADC Status and Control Register (ADSCR) . . . . . . . . . . . . . . 477
26-3 ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
26-4 ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . . . .480
27-1 BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
27-2 BDLC Operating Modes State Diagram . . . . . . . . . . . . . . . . . 487
27-3 BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
27-4 BDLC Rx Digital Filter Block Diagram . . . . . . . . . . . . . . . . . . 491
27-5 J1850 Bus Message Format (VPW) . . . . . . . . . . . . . . . . . . . . 493
27-6 J1850 VPW Symbols with Nominal Symbol Times. . . . . . . . . 498
27-7 J1850 VPW Received Passive Symbol Times . . . . . . . . . . . . 501
27-8 J1850 VPW Received Passive EOF and IFS Symbol Times .502
27-9 J1850 VPW Received Active Symbol Times . . . . . . . . . . . . . 503
27-10 J1850 VPW Received BREAK Symbol Times . . . . . . . . . . . .504
27-11 J1850 VPW Bitwise Arbitrations . . . . . . . . . . . . . . . . . . . . . . . 505
27-12 BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
List of Figures
. . . . . . . . . . . . . . . . . . . . 433
MC68HC908AZ60A — Rev 2.0
MOTOROLA