XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 513

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

27.7.1 BDLC Analog and Roundtrip Delay Register
MC68HC908AZ60A — Rev 2.0
MOTOROLA
NOTE:
Address:
Figure 27-15. BDLC Analog and Roundtrip Delay Register (BARD)
This register programs the BDLC to compensate for various delays of
different external transceivers. The default delay value is16 µs.
Timing adjustments from 9 µs to 24 µs in steps of 1 µs are available. The
BARD register can be written only once after each reset, after which they
become read-only bits. The register may be read at any time.
ATE — Analog Transceiver Enable Bit
This device does not contain an on-board transceiver. This bit should be
programmed to a logic 0 for proper operation.
RXPOL — Receive Pin Polarity Bit
Reset:
Read:
Write:
The analog transceiver enable (ATE) bit is used to select either the
on-board or an off-chip analog transceiver.
The receive pin polarity (RXPOL) bit is used to select the polarity of
an incoming signal on the receive pin. Some external analog
transceivers invert the receive signal from the J1850 bus before
feeding it back to the digital receive pin.
1 = Select on-board analog transceiver
0 = Select off-chip analog transceiver
1 = Select normal/true polarity; true non-inverted signal from the
0 = Select inverted polarity, where an external transceiver inverts
$003B
Bit 7
ATE
J1850 bus; for example, the external transceiver does not
invert the receive signal
the receive signal from the J1850 bus
R
1
Byte Data Link Controller (BDLC)
= Reserved
RXPOL
6
1
R
5
0
0
R
4
0
0
BO3
3
0
Byte Data Link Controller (BDLC)
BO2
2
1
BDLC CPU Interface
BO1
1
1
Technical Data
Bit 0
BO0
1
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